[media] exynos4-is: Add support for all required clocks
authorMarek Szyprowski <m.szyprowski@samsung.com>
Wed, 31 Aug 2016 13:25:16 +0000 (10:25 -0300)
committerMauro Carvalho Chehab <mchehab@s-opensource.com>
Thu, 22 Sep 2016 13:13:53 +0000 (10:13 -0300)
This patch adds 3 more clocks to Exynos4 ISP driver. Enabling them is
needed to make the hardware operational. Till now it worked only because
those clocks were registered with IGNORE_UNUSED flag and were enabled
by default after SoC reset.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Documentation/devicetree/bindings/media/exynos4-fimc-is.txt
drivers/media/platform/exynos4-is/fimc-is.c
drivers/media/platform/exynos4-is/fimc-is.h

index 55c9ad6f9599e886b55f643174b1a453a9359aa5..32ced99d4244d6f8cc3d324fca50a790ed504500 100644 (file)
@@ -16,9 +16,10 @@ Required properties:
 - clocks       : list of clock specifiers, corresponding to entries in
                  clock-names property;
 - clock-names  : must contain "ppmuispx", "ppmuispx", "lite0", "lite1"
-                 "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "uart",
-                 "ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "aclk200",
-                 "div_aclk200", "aclk400mcuisp", "div_aclk400mcuisp" entries,
+                 "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "gicisp",
+                 "pwm_isp", "mcuctl_isp", "uart", "ispdiv0", "ispdiv1",
+                 "mcuispdiv0", "mcuispdiv1", "aclk200", "div_aclk200",
+                 "aclk400mcuisp", "div_aclk400mcuisp" entries,
                  matching entries in the clocks property.
 pmu subnode
 -----------
index 13c779de79fdf7b24fc1b07b90a9b0f798685ceb..313ab10dbb9496b7e400f6a3e1933d2934b87415 100644 (file)
@@ -52,6 +52,9 @@ static char *fimc_is_clocks[ISS_CLKS_MAX] = {
        [ISS_CLK_DRC]                   = "drc",
        [ISS_CLK_FD]                    = "fd",
        [ISS_CLK_MCUISP]                = "mcuisp",
+       [ISS_CLK_GICISP]                = "gicisp",
+       [ISS_CLK_PWM_ISP]               = "pwm_isp",
+       [ISS_CLK_MCUCTL_ISP]            = "mcuctl_isp",
        [ISS_CLK_UART]                  = "uart",
        [ISS_CLK_ISP_DIV0]              = "ispdiv0",
        [ISS_CLK_ISP_DIV1]              = "ispdiv1",
index 3a82c6a214c7df7b25f247d57829b5071de788bd..ee05da034aa1c99adbb57cad46c841a659afd12e 100644 (file)
@@ -77,6 +77,9 @@ enum {
        ISS_CLK_DRC,
        ISS_CLK_FD,
        ISS_CLK_MCUISP,
+       ISS_CLK_GICISP,
+       ISS_CLK_PWM_ISP,
+       ISS_CLK_MCUCTL_ISP,
        ISS_CLK_UART,
        ISS_GATE_CLKS_MAX,
        ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,