#include "../comedidev.h"
#include "comedi_fc.h"
-#include "mite.h"
#define NI6527_DI_REG(x) (0x00 + (x))
#define NI6527_DO_REG(x) (0x03 + (x))
};
struct ni6527_private {
- struct mite_struct *mite;
+ void __iomem *mmio_base;
unsigned int filter_interval;
unsigned int filter_enable;
};
unsigned int val)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
if (val != devpriv->filter_interval) {
writeb(val & 0xff, mmio + NI6527_FILT_INTERVAL_REG(0));
unsigned int val)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
writeb(val & 0xff, mmio + NI6527_FILT_ENA_REG(0));
writeb((val >> 8) & 0xff, mmio + NI6527_FILT_ENA_REG(1));
unsigned int *data)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
unsigned int val;
val = readb(mmio + NI6527_DI_REG(0));
unsigned int *data)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
unsigned int mask;
mask = comedi_dio_update_state(s, data);
struct comedi_device *dev = d;
struct ni6527_private *devpriv = dev->private;
struct comedi_subdevice *s = dev->read_subdev;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
unsigned int status;
status = readb(mmio + NI6527_STATUS_REG);
struct comedi_subdevice *s)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
writeb(NI6527_CTRL_ENABLE_IRQS, mmio + NI6527_CTRL_REG);
struct comedi_subdevice *s)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
writeb(NI6527_CTRL_DISABLE_IRQS, mmio + NI6527_CTRL_REG);
unsigned int falling)
{
struct ni6527_private *devpriv = dev->private;
- void __iomem *mmio = devpriv->mite->daq_io_addr;
+ void __iomem *mmio = devpriv->mmio_base;
/* enable rising-edge detection channels */
writeb(rising & 0xff, mmio + NI6527_RISING_EDGE_REG(0));
if (!devpriv)
return -ENOMEM;
- devpriv->mite = mite_alloc(pcidev);
- if (!devpriv->mite)
+ devpriv->mmio_base = pci_ioremap_bar(pcidev, 1);
+ if (!devpriv->mmio_base)
return -ENOMEM;
- ret = mite_setup(devpriv->mite);
- if (ret < 0) {
- dev_err(dev->class_dev, "error setting up mite\n");
- return ret;
- }
-
/* make sure this is actually a 6527 device */
- if (readb(devpriv->mite->daq_io_addr + NI6527_ID_REG) != 0x27)
+ if (readb(devpriv->mmio_base + NI6527_ID_REG) != 0x27)
return -ENODEV;
ret = comedi_alloc_subdevices(dev, 3);
ni6527_set_filter_enable(dev, 0);
writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
- devpriv->mite->daq_io_addr + NI6527_CLR_REG);
+ devpriv->mmio_base + NI6527_CLR_REG);
writeb(NI6527_CTRL_DISABLE_IRQS,
- devpriv->mite->daq_io_addr + NI6527_CTRL_REG);
+ devpriv->mmio_base + NI6527_CTRL_REG);
- ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
+ ret = request_irq(pcidev->irq, ni6527_interrupt,
IRQF_SHARED, dev->board_name, dev);
if (ret < 0)
dev_warn(dev->class_dev, "irq not available\n");
else
- dev->irq = mite_irq(devpriv->mite);
+ dev->irq = pcidev->irq;
return 0;
}
{
struct ni6527_private *devpriv = dev->private;
- if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
+ if (devpriv && devpriv->mmio_base)
writeb(NI6527_CTRL_DISABLE_IRQS,
- devpriv->mite->daq_io_addr + NI6527_CTRL_REG);
+ devpriv->mmio_base + NI6527_CTRL_REG);
if (dev->irq)
free_irq(dev->irq, dev);
- if (devpriv && devpriv->mite) {
- mite_unsetup(devpriv->mite);
- mite_free(devpriv->mite);
- }
comedi_pci_disable(dev);
}