Changes since U-Boot 1.1.1:
======================================================================
+* Patches by Lars Munch, 12 Jul 2004:
+ - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
+ board specific
+ - split out the LXT971A PHY from ns_9750_eth.h
+ - split the dm9161 phy part out of at91rm9200_ether.c
+
* Patch by Andreas Engel, 12 Jul 2004:
Replaced hardcoded PL011 clock frequency with config variable.
Fixed wrong CONFIG_CMD_DFL doc.
LIB = lib$(BOARD).a
-OBJS := at91rm9200dk.o flash.o
+OBJS := at91rm9200dk.o at45.o dm9161.o flash.o
SOBJS :=
$(LIB): $(OBJS) $(SOBJS)
--- /dev/null
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY 200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */
+
+void AT91F_SpiInit(void) {
+
+/*-------------------------------------------------------------------*/
+/* SPI DataFlash Init */
+/*-------------------------------------------------------------------*/
+ /* Configure PIOs */
+ AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+ AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+ AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+ AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+ /* Enable CLock */
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+ /* Reset the SPI */
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+ /* Configure SPI in Master Mode with No CS selected !!! */
+ AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+ /* Configure CS0 and CS3 */
+ *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+ DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+ *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+ DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+}
+
+void AT91F_SpiEnable(int cs) {
+ switch(cs) {
+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
+ break;
+ case 3: /* Configure SPI CS3 for Serial DataFlash Card */
+ /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
+ AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */
+ AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */
+ /* Clear Output */
+ AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+ /* Configure PCS */
+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ break;
+ }
+
+ /* SPI_Enable */
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+/*----------------------------------------------------------------------------*/
+/* \fn AT91F_SpiWrite */
+/* \brief Set the PDC registers for a transfert */
+/*----------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+ unsigned int timeout;
+
+ pDesc->state = BUSY;
+
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+ /* Initialize the Transmit and Receive Pointer */
+ AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+ AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+ /* Intialize the Transmit and Receive Counters */
+ AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+ AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+ if ( pDesc->tx_data_size != 0 ) {
+ /* Initialize the Next Transmit and Next Receive Pointer */
+ AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+ AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+ /* Intialize the Next Transmit and Next Receive Counters */
+ AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+ AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+ }
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+ timeout = 0;
+
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+ while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ pDesc->state = IDLE;
+
+ if (timeout >= CFG_SPI_WRITE_TOUT){
+ printf("Error Timeout\n\r");
+ return DATAFLASH_ERROR;
+ }
+
+ return DATAFLASH_OK;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashSendCommand */
+/* \brief Generic function to send a command to the dataflash */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress)
+{
+ unsigned int adr;
+
+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* process the address to obtain page address and byte address */
+ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
+
+ /* fill the command buffer */
+ pDataFlash->pDataFlashDesc->command[0] = OpCode;
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
+ } else {
+ pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
+ pDataFlash->pDataFlashDesc->command[4] = 0;
+ }
+ pDataFlash->pDataFlashDesc->command[5] = 0;
+ pDataFlash->pDataFlashDesc->command[6] = 0;
+ pDataFlash->pDataFlashDesc->command[7] = 0;
+
+ /* Initialize the SpiData structure for the spi write fuction */
+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ;
+
+ /* send the command and read the data */
+ return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashGetStatus */
+/* \brief Read the status register of the dataflash */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+ AT91S_DataFlashStatus status;
+
+ /* if a transfert is in progress ==> return 0 */
+ if( (pDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* first send the read status command (D7H) */
+ pDesc->command[0] = DB_STATUS;
+ pDesc->command[1] = 0;
+
+ pDesc->DataFlash_state = GET_STATUS;
+ pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
+ pDesc->tx_cmd_pt = pDesc->command ;
+ pDesc->rx_cmd_pt = pDesc->command ;
+ pDesc->rx_cmd_size = 2 ;
+ pDesc->tx_cmd_size = 2 ;
+ status = AT91F_SpiWrite (pDesc);
+
+ pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+ return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashWaitReady */
+/* \brief wait for dataflash ready (bit7 of the status register == 1) */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
+{
+ pDataFlashDesc->DataFlash_state = IDLE;
+
+ do {
+ AT91F_DataFlashGetStatus(pDataFlashDesc);
+ timeout--;
+ } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
+
+ if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+ return DATAFLASH_ERROR;
+
+ return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashContinuousRead */
+/* Object : Continuous stream Read */
+/* Input Parameters : DataFlash Service */
+/* : <src> = dataflash address */
+/* : <*dataBuffer> = data buffer pointer */
+/* : <sizeToRead> = data buffer size */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead )
+{
+ AT91S_DataFlashStatus status;
+ /* Test the size to read in the device */
+ if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+ return DATAFLASH_MEMORY_OVERFLOW;
+
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+ status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+ /* Send the command to the dataflash */
+ return(status);
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashPagePgmBuf */
+/* Object : Main memory page program through buffer 1 or buffer 2 */
+/* Input Parameters : DataFlash Service */
+/* : <*src> = Source buffer */
+/* : <dest> = dataflash destination address */
+/* : <SizeToWrite> = data buffer size */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite)
+{
+ int cmdsize;
+ pDataFlash->pDataFlashDesc->tx_data_pt = src ;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+ pDataFlash->pDataFlashDesc->rx_data_pt = src;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+ cmdsize = 4;
+ /* Send the command to the dataflash */
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_MainMemoryToBufferTransfert */
+/* Object : Read a page in the SRAM Buffer 1 or 2 */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int page)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+ return DATAFLASH_BAD_COMMAND;
+
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*----------------------------------------------------------------------------- */
+/* Function Name : AT91F_DataFlashWriteBuffer */
+/* Object : Write data to the internal sram buffer 1 or 2 */
+/* Input Parameters : DataFlash Service */
+/* : <BufferCommand> = command to write buffer1 or buffer2 */
+/* : <*dataBuffer> = data buffer to write */
+/* : <bufferAddress> = address in the internal buffer */
+/* : <SizeToWrite> = data buffer size */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite )
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
+ return DATAFLASH_BAD_COMMAND;
+
+ /* buffer address must be lower than page size */
+ if (bufferAddress > pDataFlash->pDevice->pages_size)
+ return DATAFLASH_BAD_ADDRESS;
+
+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* Send first Write Command */
+ pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+ pDataFlash->pDataFlashDesc->command[1] = 0;
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ pDataFlash->pDataFlashDesc->command[2] = 0;
+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
+ pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
+ cmdsize = 5;
+ } else {
+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
+ pDataFlash->pDataFlashDesc->command[4] = 0;
+ cmdsize = 4;
+ }
+
+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
+
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+
+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_PageErase */
+/* Object : Erase a page */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_BlockErase */
+/* Object : Erase a Block */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_WriteBufferToMain */
+/* Object : Write buffer to the main memory */
+/* Input Parameters : DataFlash Service */
+/* : <BufferCommand> = command to send to buffer1 or buffer2 */
+/* : <dest> = main memory address */
+/* Return value : State of the dataflash */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest )
+{
+ int cmdsize;
+ /* Test if the buffer command is correct */
+ if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+ return DATAFLASH_BAD_COMMAND;
+
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ /* Send the command to the dataflash */
+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_PartialPageWrite */
+/* Object : Erase partielly a page */
+/* Input Parameters : <page> = page number */
+/* : <AdrInpage> = adr to begin the fading */
+/* : <length> = Number of bytes to erase */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size)
+{
+ unsigned int page;
+ unsigned int AdrInPage;
+
+ page = dest / (pDataFlash->pDevice->pages_size);
+ AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+ /* Read the contents of the page in the Sram Buffer */
+ AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+ /*Update the SRAM buffer */
+ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+ /* Erase page if a 128 Mbits device */
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ AT91F_PageErase(pDataFlash, page);
+ /* Rewrite the modified Sram Buffer in the main memory */
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+ }
+
+ /* Rewrite the modified Sram Buffer in the main memory */
+ return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashWrite */
+/* Object : */
+/* Input Parameters : <*src> = Source buffer */
+/* : <dest> = dataflash adress */
+/* : <size> = data buffer size */
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest,
+ int size )
+{
+ unsigned int length;
+ unsigned int page;
+ unsigned int status;
+
+ AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+ if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+ return DATAFLASH_MEMORY_OVERFLOW;
+
+ /* If destination does not fit a page start address */
+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
+ length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
+
+ if (size < length)
+ length = size;
+
+ if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+ /* Update size, source and destination pointers */
+ size -= length;
+ dest += length;
+ src += length;
+ }
+
+ while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+ /* program dataflash page */
+ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+ status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+ status = AT91F_PageErase(pDataFlash, page);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+ if (!status)
+ return DATAFLASH_ERROR;
+
+ status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
+ if(!status)
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+ /* Update size, source and destination pointers */
+ size -= pDataFlash->pDevice->pages_size ;
+ dest += pDataFlash->pDevice->pages_size ;
+ src += pDataFlash->pDevice->pages_size ;
+ }
+
+ /* If still some bytes to read */
+ if ( size > 0 ) {
+ /* program dataflash page */
+ if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+ }
+ return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashRead */
+/* Object : Read a block in dataflash */
+/* Input Parameters : */
+/* Return value : */
+/*------------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+ AT91PS_DataFlash pDataFlash,
+ unsigned long addr,
+ unsigned long size,
+ char *buffer)
+{
+ unsigned long SizeToRead;
+
+ AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+ if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ return -1;
+
+ while (size) {
+ SizeToRead = (size < 0x8000)? size:0x8000;
+
+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ return -1;
+
+ if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+ return -1;
+
+ size -= SizeToRead;
+ addr += SizeToRead;
+ buffer += SizeToRead;
+ }
+
+ return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataflashProbe */
+/* Object : */
+/* Input Parameters : */
+/* Return value : Dataflash status register */
+/*------------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
+ AT91F_SpiEnable(cs);
+ AT91F_DataFlashGetStatus(pDesc);
+ return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dm9161.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * dm9161_IsPhyConnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * TRUE - if id read successfully
+ * FALSE- if error
+ */
+static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+ unsigned short Id1, Id2;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+ at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+ ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+ return TRUE;
+
+ return FALSE;
+}
+
+/*
+ * Name:
+ * dm9161_GetLinkSpeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+ unsigned short stat1, stat2;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+ return FALSE;
+
+ if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
+ return FALSE;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+ return FALSE;
+
+ if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+ /*set Emac for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+ /*set MII for 100BaseTX and Half Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ return TRUE;
+ }
+
+ if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+ /*set MII for 10BaseT and Half Duplex */
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ return TRUE;
+ }
+ return FALSE;
+}
+
+
+/*
+ * Name:
+ * dm9161_InitPhy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+ UCHAR ret = TRUE;
+ unsigned short IntValue;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+
+ if (!dm9161_GetLinkSpeed (p_mac)) {
+ /* Try another time */
+ ret = dm9161_GetLinkSpeed (p_mac);
+ }
+
+ /* Disable PHY Interrupts */
+ at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+ /* clear FDX, SPD, Link, INTR masks */
+ IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
+ DM9161_LINK_MASK | DM9161_INTR_MASK);
+ at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ return (ret);
+}
+
+
+/*
+ * Name:
+ * dm9161_AutoNegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * TRUE - if link status set successfully
+ * FALSE - if link status not set
+ */
+static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+ unsigned short PhyAnar;
+ unsigned short PhyAnalpar;
+
+ /* Set dm9161 control register */
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+ value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
+ value |= DM9161_ISOLATE; /* Electrically isolate PHY */
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+
+ /* Set the Auto_negotiation Advertisement Register */
+ /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+ PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+ DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+ return FALSE;
+
+ /* Read the Control Register */
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+
+ value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+ /* Restart Auto_negotiation */
+ value |= DM9161_RESTART_AUTONEG;
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+
+ /*check AutoNegotiate complete */
+ udelay (10000);
+ at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+ if (!(value & DM9161_AUTONEG_COMP))
+ return FALSE;
+
+ /* Get the AutoNeg Link partner base page */
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+ return FALSE;
+
+ if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+ /*set MII for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return TRUE;
+ }
+ return FALSE;
+}
+
+
+/*
+ * Name:
+ * at91rm92000_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = dm9161_InitPhy;
+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
START = start.o
OBJS = serial.o interrupts.o cpu.o \
- at91rm9200_ether.o at45.o
+ at91rm9200_ether.o
all: .depend $(START) $(LIB)
+++ /dev/null
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
-the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS (0xC << 16)
-#define DATAFLASH_TCHS (0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY 200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */
-
-void AT91F_SpiInit(void) {
-
-/*-------------------------------------------------------------------*/
-/* SPI DataFlash Init */
-/*-------------------------------------------------------------------*/
- /* Configure PIOs */
- AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
- AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
- AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
- AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
- /* Enable CLock */
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
- /* Reset the SPI */
- AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
- /* Configure SPI in Master Mode with No CS selected !!! */
- AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
- /* Configure CS0 and CS3 */
- *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
- DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
- *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
- DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-}
-
-void AT91F_SpiEnable(int cs) {
- switch(cs) {
- case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
- AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
- break;
- case 3: /* Configure SPI CS3 for Serial DataFlash Card */
- /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
- AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */
- AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */
- /* Clear Output */
- AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
- /* Configure PCS */
- AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
- break;
- }
-
- /* SPI_Enable */
- AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-/*----------------------------------------------------------------------------*/
-/* \fn AT91F_SpiWrite */
-/* \brief Set the PDC registers for a transfert */
-/*----------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
- unsigned int timeout;
-
- pDesc->state = BUSY;
-
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
- /* Initialize the Transmit and Receive Pointer */
- AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
- AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
- /* Intialize the Transmit and Receive Counters */
- AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
- AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
- if ( pDesc->tx_data_size != 0 ) {
- /* Initialize the Next Transmit and Next Receive Pointer */
- AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
- AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
- /* Intialize the Next Transmit and Next Receive Counters */
- AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
- AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
- }
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked();
- timeout = 0;
-
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
- while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
- pDesc->state = IDLE;
-
- if (timeout >= CFG_SPI_WRITE_TOUT){
- printf("Error Timeout\n\r");
- return DATAFLASH_ERROR;
- }
-
- return DATAFLASH_OK;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashSendCommand */
-/* \brief Generic function to send a command to the dataflash */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
- AT91PS_DataFlash pDataFlash,
- unsigned char OpCode,
- unsigned int CmdSize,
- unsigned int DataflashAddress)
-{
- unsigned int adr;
-
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* process the address to obtain page address and byte address */
- adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
-
- /* fill the command buffer */
- pDataFlash->pDataFlashDesc->command[0] = OpCode;
- if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
- pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
- } else {
- pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
- pDataFlash->pDataFlashDesc->command[4] = 0;
- }
- pDataFlash->pDataFlashDesc->command[5] = 0;
- pDataFlash->pDataFlashDesc->command[6] = 0;
- pDataFlash->pDataFlashDesc->command[7] = 0;
-
- /* Initialize the SpiData structure for the spi write fuction */
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ;
-
- /* send the command and read the data */
- return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashGetStatus */
-/* \brief Read the status register of the dataflash */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
-{
- AT91S_DataFlashStatus status;
-
- /* if a transfert is in progress ==> return 0 */
- if( (pDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* first send the read status command (D7H) */
- pDesc->command[0] = DB_STATUS;
- pDesc->command[1] = 0;
-
- pDesc->DataFlash_state = GET_STATUS;
- pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
- pDesc->tx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_size = 2 ;
- pDesc->tx_cmd_size = 2 ;
- status = AT91F_SpiWrite (pDesc);
-
- pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
-
- return status;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn AT91F_DataFlashWaitReady */
-/* \brief wait for dataflash ready (bit7 of the status register == 1) */
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
-{
- pDataFlashDesc->DataFlash_state = IDLE;
-
- do {
- AT91F_DataFlashGetStatus(pDataFlashDesc);
- timeout--;
- } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
-
- if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
- return DATAFLASH_ERROR;
-
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashContinuousRead */
-/* Object : Continuous stream Read */
-/* Input Parameters : DataFlash Service */
-/* : <src> = dataflash address */
-/* : <*dataBuffer> = data buffer pointer */
-/* : <sizeToRead> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
- int src,
- unsigned char *dataBuffer,
- int sizeToRead )
-{
- AT91S_DataFlashStatus status;
- /* Test the size to read in the device */
- if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
- return DATAFLASH_MEMORY_OVERFLOW;
-
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
-
- status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
- /* Send the command to the dataflash */
- return(status);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashPagePgmBuf */
-/* Object : Main memory page program through buffer 1 or buffer 2 */
-/* Input Parameters : DataFlash Service */
-/* : <*src> = Source buffer */
-/* : <dest> = dataflash destination address */
-/* : <SizeToWrite> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int SizeToWrite)
-{
- int cmdsize;
- pDataFlash->pDataFlashDesc->tx_data_pt = src ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->rx_data_pt = src;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
-
- cmdsize = 4;
- /* Send the command to the dataflash */
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_MainMemoryToBufferTransfert */
-/* Object : Read a page in the SRAM Buffer 1 or 2 */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int page)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
- return DATAFLASH_BAD_COMMAND;
-
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*----------------------------------------------------------------------------- */
-/* Function Name : AT91F_DataFlashWriteBuffer */
-/* Object : Write data to the internal sram buffer 1 or 2 */
-/* Input Parameters : DataFlash Service */
-/* : <BufferCommand> = command to write buffer1 or buffer2 */
-/* : <*dataBuffer> = data buffer to write */
-/* : <bufferAddress> = address in the internal buffer */
-/* : <SizeToWrite> = data buffer size */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned char *dataBuffer,
- unsigned int bufferAddress,
- int SizeToWrite )
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
- return DATAFLASH_BAD_COMMAND;
-
- /* buffer address must be lower than page size */
- if (bufferAddress > pDataFlash->pDevice->pages_size)
- return DATAFLASH_BAD_ADDRESS;
-
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
- return DATAFLASH_BUSY;
-
- /* Send first Write Command */
- pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
- pDataFlash->pDataFlashDesc->command[1] = 0;
- if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[2] = 0;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- cmdsize = 5;
- } else {
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- pDataFlash->pDataFlashDesc->command[4] = 0;
- cmdsize = 4;
- }
-
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
-
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
-
- return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_PageErase */
-/* Object : Erase a page */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PageErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int page)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_BlockErase */
-/* Object : Erase a Block */
-/* Input Parameters : DataFlash Service */
-/* : Page concerned */
-/* : */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_BlockErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int block)
-{
- int cmdsize;
- /* Test if the buffer command is legal */
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_WriteBufferToMain */
-/* Object : Write buffer to the main memory */
-/* Input Parameters : DataFlash Service */
-/* : <BufferCommand> = command to send to buffer1 or buffer2 */
-/* : <dest> = main memory address */
-/* Return value : State of the dataflash */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int dest )
-{
- int cmdsize;
- /* Test if the buffer command is correct */
- if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
- (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
- return DATAFLASH_BAD_COMMAND;
-
- /* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
- cmdsize = 4;
- if (pDataFlash->pDevice->pages_number >= 16384)
- cmdsize = 5;
- /* Send the command to the dataflash */
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_PartialPageWrite */
-/* Object : Erase partielly a page */
-/* Input Parameters : <page> = page number */
-/* : <AdrInpage> = adr to begin the fading */
-/* : <length> = Number of bytes to erase */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int size)
-{
- unsigned int page;
- unsigned int AdrInPage;
-
- page = dest / (pDataFlash->pDevice->pages_size);
- AdrInPage = dest % (pDataFlash->pDevice->pages_size);
-
- /* Read the contents of the page in the Sram Buffer */
- AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- /*Update the SRAM buffer */
- AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Erase page if a 128 Mbits device */
- if (pDataFlash->pDevice->pages_number >= 16384) {
- AT91F_PageErase(pDataFlash, page);
- /* Rewrite the modified Sram Buffer in the main memory */
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- }
-
- /* Rewrite the modified Sram Buffer in the main memory */
- return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashWrite */
-/* Object : */
-/* Input Parameters : <*src> = Source buffer */
-/* : <dest> = dataflash adress */
-/* : <size> = data buffer size */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size )
-{
- unsigned int length;
- unsigned int page;
- unsigned int status;
-
- AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
- if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
- return DATAFLASH_MEMORY_OVERFLOW;
-
- /* If destination does not fit a page start address */
- if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
- length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
-
- if (size < length)
- length = size;
-
- if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Update size, source and destination pointers */
- size -= length;
- dest += length;
- src += length;
- }
-
- while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
- /* program dataflash page */
- page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
-
- status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- status = AT91F_PageErase(pDataFlash, page);
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- if (!status)
- return DATAFLASH_ERROR;
-
- status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
- if(!status)
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
- /* Update size, source and destination pointers */
- size -= pDataFlash->pDevice->pages_size ;
- dest += pDataFlash->pDevice->pages_size ;
- src += pDataFlash->pDevice->pages_size ;
- }
-
- /* If still some bytes to read */
- if ( size > 0 ) {
- /* program dataflash page */
- if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
- return DATAFLASH_ERROR;
-
- AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
- }
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataFlashRead */
-/* Object : Read a block in dataflash */
-/* Input Parameters : */
-/* Return value : */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
- AT91PS_DataFlash pDataFlash,
- unsigned long addr,
- unsigned long size,
- char *buffer)
-{
- unsigned long SizeToRead;
-
- AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
- if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
- return -1;
-
- while (size) {
- SizeToRead = (size < 0x8000)? size:0x8000;
-
- if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
- return -1;
-
- if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
- return -1;
-
- size -= SizeToRead;
- addr += SizeToRead;
- buffer += SizeToRead;
- }
-
- return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataflashProbe */
-/* Object : */
-/* Input Parameters : */
-/* Return value : Dataflash status register */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
-{
- AT91F_SpiEnable(cs);
- AT91F_DataFlashGetStatus(pDesc);
- return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
-}
-
-#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/* structure to interface the PHY */
-AT91S_PhyOps AT91S_Dm9161Ops;
-AT91PS_PhyOps pPhyOps;
+AT91S_PhyOps PhyOps;
AT91PS_EMAC p_mac;
-/*************************** Phy layer functions ************************/
-/** functions to interface the DAVICOM 10/100Mbps ethernet phy **********/
-
-/*
- * Name:
- * dm9161_IsPhyConnected
- * Description:
- * Reads the 2 PHY ID registers
- * Arguments:
- * p_mac - pointer to AT91S_EMAC struct
- * Return value:
- * TRUE - if id read successfully
- * FALSE- if error
- */
-static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
-{
- unsigned short Id1, Id2;
-
- at91rm9200_EmacEnableMDIO (p_mac);
- at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
- at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
- at91rm9200_EmacDisableMDIO (p_mac);
-
- if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
- ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
- return TRUE;
-
- return FALSE;
-}
-
-/*
- * Name:
- * dm9161_GetLinkSpeed
- * Description:
- * Link parallel detection status of MAC is checked and set in the
- * MAC configuration registers
- * Arguments:
- * p_mac - pointer to MAC
- * Return value:
- * TRUE - if link status set succesfully
- * FALSE - if link status not set
- */
-static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
- unsigned short stat1, stat2;
-
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
- return FALSE;
-
- if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
- return FALSE;
-
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
- return FALSE;
-
- if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
- /*set Emac for 100BaseTX and Full Duplex */
- p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
- return TRUE;
- }
-
- if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
- /*set MII for 10BaseT and Full Duplex */
- p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
- ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
- | AT91C_EMAC_FD;
- return TRUE;
- }
-
- if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
- /*set MII for 100BaseTX and Half Duplex */
- p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
- ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
- | AT91C_EMAC_SPD;
- return TRUE;
- }
-
- if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
- /*set MII for 10BaseT and Half Duplex */
- p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
- return TRUE;
- }
- return FALSE;
-}
-
-
-/*
- * Name:
- * dm9161_InitPhy
- * Description:
- * MAC starts checking its link by using parallel detection and
- * Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- * p_mac - pointer to struct AT91S_EMAC
- * Return value:
- * TRUE - if link status set succesfully
- * FALSE - if link status not set
- */
-static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
-{
- UCHAR ret = TRUE;
- unsigned short IntValue;
-
- at91rm9200_EmacEnableMDIO (p_mac);
-
- if (!dm9161_GetLinkSpeed (p_mac)) {
- /* Try another time */
- ret = dm9161_GetLinkSpeed (p_mac);
- }
-
- /* Disable PHY Interrupts */
- at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
- /* clear FDX, SPD, Link, INTR masks */
- IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
- DM9161_LINK_MASK | DM9161_INTR_MASK);
- at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
- at91rm9200_EmacDisableMDIO (p_mac);
-
- return (ret);
-}
-
-
-/*
- * Name:
- * dm9161_AutoNegotiate
- * Description:
- * MAC Autonegotiates with the partner status of same is set in the
- * MAC configuration registers
- * Arguments:
- * dev - pointer to struct net_device
- * Return value:
- * TRUE - if link status set successfully
- * FALSE - if link status not set
- */
-static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
- unsigned short value;
- unsigned short PhyAnar;
- unsigned short PhyAnalpar;
-
- /* Set dm9161 control register */
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
- return FALSE;
- value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
- value |= DM9161_ISOLATE; /* Electrically isolate PHY */
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
- return FALSE;
-
- /* Set the Auto_negotiation Advertisement Register */
- /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
- PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
- DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
- return FALSE;
-
- /* Read the Control Register */
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
- return FALSE;
-
- value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
- return FALSE;
- /* Restart Auto_negotiation */
- value |= DM9161_RESTART_AUTONEG;
- if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
- return FALSE;
-
- /*check AutoNegotiate complete */
- udelay (10000);
- at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
- if (!(value & DM9161_AUTONEG_COMP))
- return FALSE;
-
- /* Get the AutoNeg Link partner base page */
- if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
- return FALSE;
-
- if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
- /*set MII for 100BaseTX and Full Duplex */
- p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
- return TRUE;
- }
-
- if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
- /*set MII for 10BaseT and Full Duplex */
- p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
- ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
- | AT91C_EMAC_FD;
- return TRUE;
- }
- return FALSE;
-}
-
-
/*********** EMAC Phy layer Management functions *************************/
/*
* Name:
* Return value:
* none
*/
-static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
+void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
{
/* Mac CTRL reg set for MDIO enable */
p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
* Return value:
* none
*/
-static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
+void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
{
/* Mac CTRL reg set for MDIO disable */
p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
* Return value:
* TRUE - if data read successfully
*/
-static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
+UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
unsigned char RegisterAddress,
unsigned short *pInput)
{
* Return value:
* TRUE - if data read successfully
*/
-static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
+UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
unsigned char RegisterAddress,
unsigned short *pOutput)
{
return TRUE;
}
-/*
- * Name:
- * at91rm92000_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm92000_GetPhyInterface (void)
-{
- AT91S_Dm9161Ops.Init = dm9161_InitPhy;
- AT91S_Dm9161Ops.IsPhyConnected = dm9161_IsPhyConnected;
- AT91S_Dm9161Ops.GetLinkSpeed = dm9161_GetLinkSpeed;
- AT91S_Dm9161Ops.AutoNegotiate = dm9161_AutoNegotiate;
-
- pPhyOps = (AT91PS_PhyOps) & AT91S_Dm9161Ops;
-}
-
rbf_t *rbfdt;
rbf_t *rbfp;
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
- at91rm92000_GetPhyInterface ();
+ at91rm92000_GetPhyInterface (& PhyOps);
- if (!pPhyOps->IsPhyConnected (p_mac))
+ if (!PhyOps.IsPhyConnected (p_mac))
printf ("PHY not connected!!\n\r");
/* MII management start from here */
if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
- if (!(ret = pPhyOps->Init (p_mac))) {
+ if (!(ret = PhyOps.Init (p_mac))) {
printf ("MAC: error during MII initialization\n");
return 0;
}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include "dm9161.h"
#define FALSE 0
#define TRUE 1
/****************** function prototypes **********************/
/* MII functions */
-static void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
-static void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
-static UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
-static UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
-void at91rm92000_GetPhyInterface(void );
+void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
+void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
+UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
+UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
+void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops);
#endif /* AT91RM9200_ETHERNET */
--- /dev/null
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ * [2] Intel LXT971 Datasheet #249414 Rev. 02
+ * [3] NS7520 Linux Ethernet Driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef __LXT971A_H__
+#define __LXT971A_H__
+
+/* PHY definitions (LXT971A) [2] */
+#define PHY_COMMON_CTRL (0x00)
+#define PHY_COMMON_STAT (0x01)
+#define PHY_COMMON_ID1 (0x02)
+#define PHY_COMMON_ID2 (0x03)
+#define PHY_COMMON_AUTO_ADV (0x04)
+#define PHY_COMMON_AUTO_LNKB (0x05)
+#define PHY_COMMON_AUTO_EXP (0x06)
+#define PHY_COMMON_AUTO_NEXT (0x07)
+#define PHY_COMMON_AUTO_LNKN (0x08)
+#define PHY_LXT971_PORT_CFG (0x10)
+#define PHY_LXT971_STAT2 (0x11)
+#define PHY_LXT971_INT_ENABLE (0x12)
+#define PHY_LXT971_INT_STATUS (0x13)
+#define PHY_LXT971_LED_CFG (0x14)
+#define PHY_LXT971_DIG_CFG (0x1A)
+#define PHY_LXT971_TX_CTRL (0x1E)
+
+/* CTRL PHY Control Register Bit Fields */
+#define PHY_COMMON_CTRL_RESET (0x8000)
+#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
+#define PHY_COMMON_CTRL_SPD_MA (0x2040)
+#define PHY_COMMON_CTRL_SPD_10 (0x0000)
+#define PHY_COMMON_CTRL_SPD_100 (0x2000)
+#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
+#define PHY_COMMON_CTRL_SPD_RES (0x2040)
+#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
+#define PHY_COMMON_CTRL_POWER_DN (0x0800)
+#define PHY_COMMON_CTRL_ISOLATE (0x0400)
+#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
+#define PHY_COMMON_CTRL_DUPLEX (0x0100)
+#define PHY_COMMON_CTRL_COL_TEST (0x0080)
+#define PHY_COMMON_CTRL_RES1 (0x003F)
+
+/* STAT Status Register Bit Fields */
+#define PHY_COMMON_STAT_100BT4 (0x8000)
+#define PHY_COMMON_STAT_100BXFD (0x4000)
+#define PHY_COMMON_STAT_100BXHD (0x2000)
+#define PHY_COMMON_STAT_10BTFD (0x1000)
+#define PHY_COMMON_STAT_10BTHD (0x0800)
+#define PHY_COMMON_STAT_100BT2FD (0x0400)
+#define PHY_COMMON_STAT_100BT2HD (0x0200)
+#define PHY_COMMON_STAT_EXT_STAT (0x0100)
+#define PHY_COMMON_STAT_RES1 (0x0080)
+#define PHY_COMMON_STAT_MF_PSUP (0x0040)
+#define PHY_COMMON_STAT_AN_COMP (0x0020)
+#define PHY_COMMON_STAT_RMT_FLT (0x0010)
+#define PHY_COMMON_STAT_AN_CAP (0x0008)
+#define PHY_COMMON_STAT_LNK_STAT (0x0004)
+#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
+#define PHY_COMMON_STAT_EXT_CAP (0x0001)
+
+/* AUTO_ADV Auto-neg Advert Register Bit Fields */
+#define PHY_COMMON_AUTO_ADV_NP (0x8000)
+#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
+#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
+#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
+#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
+#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
+#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
+#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
+#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
+#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
+#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
+#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
+#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
+#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
+
+/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
+#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
+#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
+#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
+#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
+#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
+#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
+#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
+#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
+#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
+#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
+#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
+#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
+#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
+#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
+
+/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
+#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
+#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
+#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
+#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
+#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
+#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
+#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
+
+/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
+#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
+#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
+#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
+#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
+#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
+#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
+
+/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
+#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
+#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
+#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
+#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
+#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
+#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
+
+/* PORT_CFG Port Configuration Register Bit Fields */
+#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
+#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
+#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
+#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
+#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
+#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
+#define PHY_LXT971_PORT_CFG_SQE (0x0200)
+#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
+#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
+#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
+#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
+#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
+#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
+#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
+
+/* STAT2 Status Register #2 Bit Fields */
+#define PHY_LXT971_STAT2_RES1 (0x8000)
+#define PHY_LXT971_STAT2_100BTX (0x4000)
+#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
+#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
+#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
+#define PHY_LXT971_STAT2_LINK (0x0400)
+#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
+#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
+#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
+#define PHY_LXT971_STAT2_RES2 (0x0040)
+#define PHY_LXT971_STAT2_POLARITY (0x0020)
+#define PHY_LXT971_STAT2_PAUSE (0x0010)
+#define PHY_LXT971_STAT2_ERROR (0x0008)
+#define PHY_LXT971_STAT2_RES3 (0x0007)
+
+/* INT_ENABLE Interrupt Enable Register Bit Fields */
+#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
+#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
+#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
+#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
+#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
+#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
+#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
+#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
+
+/* INT_STATUS Interrupt Status Register Bit Fields */
+#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
+#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
+#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
+#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
+#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
+#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
+#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
+#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
+
+/* LED_CFG Interrupt LED Configuration Register Bit Fields */
+#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
+#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
+#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
+#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
+#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
+#define PHY_LXT971_LED_CFG_RES1 (0x0001)
+
+/* only one of these values must be shifted for each SHIFT_LED? */
+#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
+#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
+#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
+#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
+#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
+#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
+#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
+#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
+#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
+#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
+#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
+#define PHY_LXT971_LED_CFG_LINK (0x0004)
+#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
+#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
+#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
+#define PHY_LXT971_LED_CFG_SPEED (0x0000)
+
+/* DIG_CFG Digitial Configuration Register Bit Fields */
+#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
+#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
+#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
+#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
+#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
+
+#define PHY_LXT971_MDIO_MAX_CLK (8000000)
+#define PHY_MDIO_MAX_CLK (2500000)
+
+/* TX_CTRL Transmit Control Register Bit Fields
+ documentation is buggy for this register, therefore setting not included */
+
+typedef enum
+{
+ PHY_NONE = 0x0000, /* no PHY detected yet */
+ PHY_LXT971A = 0x0013
+} PhyType;
+
+#endif /* __LXT971A_H__ */
#ifdef CONFIG_DRIVER_NS9750_ETHERNET
+#include "lxt971a.h"
+
#define NS9750_ETH_MODULE_BASE (0xA0600000)
#define get_eth_reg_addr(c) \
#define NS9750_ETH_RXFREE_B (0x00000002)
#define NS9750_ETH_RXFREE_A (0x00000001)
-/* PHY definitions (LXT971A) [2] */
-
-#define PHY_COMMON_CTRL (0x00)
-#define PHY_COMMON_STAT (0x01)
-#define PHY_COMMON_ID1 (0x02)
-#define PHY_COMMON_ID2 (0x03)
-#define PHY_COMMON_AUTO_ADV (0x04)
-#define PHY_COMMON_AUTO_LNKB (0x05)
-#define PHY_COMMON_AUTO_EXP (0x06)
-#define PHY_COMMON_AUTO_NEXT (0x07)
-#define PHY_COMMON_AUTO_LNKN (0x08)
-#define PHY_LXT971_PORT_CFG (0x10)
-#define PHY_LXT971_STAT2 (0x11)
-#define PHY_LXT971_INT_ENABLE (0x12)
-#define PHY_LXT971_INT_STATUS (0x13)
-#define PHY_LXT971_LED_CFG (0x14)
-#define PHY_LXT971_DIG_CFG (0x1A)
-#define PHY_LXT971_TX_CTRL (0x1E)
-
-/* CTRL PHY Control Register Bit Fields */
-
-#define PHY_COMMON_CTRL_RESET (0x8000)
-#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
-#define PHY_COMMON_CTRL_SPD_MA (0x2040)
-#define PHY_COMMON_CTRL_SPD_10 (0x0000)
-#define PHY_COMMON_CTRL_SPD_100 (0x2000)
-#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
-#define PHY_COMMON_CTRL_SPD_RES (0x2040)
-#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
-#define PHY_COMMON_CTRL_POWER_DN (0x0800)
-#define PHY_COMMON_CTRL_ISOLATE (0x0400)
-#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
-#define PHY_COMMON_CTRL_DUPLEX (0x0100)
-#define PHY_COMMON_CTRL_COL_TEST (0x0080)
-#define PHY_COMMON_CTRL_RES1 (0x003F)
-
-/* STAT Status Register Bit Fields */
-
-#define PHY_COMMON_STAT_100BT4 (0x8000)
-#define PHY_COMMON_STAT_100BXFD (0x4000)
-#define PHY_COMMON_STAT_100BXHD (0x2000)
-#define PHY_COMMON_STAT_10BTFD (0x1000)
-#define PHY_COMMON_STAT_10BTHD (0x0800)
-#define PHY_COMMON_STAT_100BT2FD (0x0400)
-#define PHY_COMMON_STAT_100BT2HD (0x0200)
-#define PHY_COMMON_STAT_EXT_STAT (0x0100)
-#define PHY_COMMON_STAT_RES1 (0x0080)
-#define PHY_COMMON_STAT_MF_PSUP (0x0040)
-#define PHY_COMMON_STAT_AN_COMP (0x0020)
-#define PHY_COMMON_STAT_RMT_FLT (0x0010)
-#define PHY_COMMON_STAT_AN_CAP (0x0008)
-#define PHY_COMMON_STAT_LNK_STAT (0x0004)
-#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
-#define PHY_COMMON_STAT_EXT_CAP (0x0001)
-
-
-/* AUTO_ADV Auto-neg Advert Register Bit Fields */
-
-#define PHY_COMMON_AUTO_ADV_NP (0x8000)
-#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
-#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
-#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
-#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
-#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
-#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
-#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
-#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
-#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
-#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
-#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
-
-/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
-
-#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
-#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
-#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
-#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
-#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
-#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
-#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
-#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
-#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
-#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
-#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
-#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
-
-/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
-
-#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
-#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
-#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
-#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
-#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
-#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
-#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
-
-/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
-
-#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
-#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
-#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
-#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
-#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
-#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
-
-/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
-
-#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
-#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
-#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
-#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
-#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
-#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
-
-/* PORT_CFG Port Configuration Register Bit Fields */
-
-#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
-#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
-#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
-#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
-#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
-#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
-#define PHY_LXT971_PORT_CFG_SQE (0x0200)
-#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
-#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
-#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
-#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
-#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
-#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
-#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
-
-/* STAT2 Status Register #2 Bit Fields */
-
-#define PHY_LXT971_STAT2_RES1 (0x8000)
-#define PHY_LXT971_STAT2_100BTX (0x4000)
-#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
-#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
-#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
-#define PHY_LXT971_STAT2_LINK (0x0400)
-#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
-#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
-#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
-#define PHY_LXT971_STAT2_RES2 (0x0040)
-#define PHY_LXT971_STAT2_POLARITY (0x0020)
-#define PHY_LXT971_STAT2_PAUSE (0x0010)
-#define PHY_LXT971_STAT2_ERROR (0x0008)
-#define PHY_LXT971_STAT2_RES3 (0x0007)
-
-/* INT_ENABLE Interrupt Enable Register Bit Fields */
-
-#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
-#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
-#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
-#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
-#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
-#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
-#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
-#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
-
-/* INT_STATUS Interrupt Status Register Bit Fields */
-
-#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
-#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
-#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
-#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
-#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
-#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
-#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
-#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
-
-/* LED_CFG Interrupt LED Configuration Register Bit Fields */
-
-#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
-#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
-#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
-#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
-#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
-#define PHY_LXT971_LED_CFG_RES1 (0x0001)
-
-/* only one of these values must be shifted for each SHIFT_LED? */
-
-#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
-#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
-#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
-#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
-#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
-#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
-#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
-#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
-#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
-#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
-#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
-#define PHY_LXT971_LED_CFG_LINK (0x0004)
-#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
-#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
-#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
-#define PHY_LXT971_LED_CFG_SPEED (0x0000)
-
-/* DIG_CFG Digitial Configuration Register Bit Fields */
-
-#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
-#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
-#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
-#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
-#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
-
-#define PHY_LXT971_MDIO_MAX_CLK (8000000)
-
-/* TX_CTRL Transmit Control Register Bit Fields
- documentation is buggy for this register, therefore setting not included */
-
-typedef enum
-{
- PHY_NONE = 0x0000, /* no PHY detected yet */
- PHY_LXT971A = 0x0013
-} PhyType;
-
-#define PHY_MDIO_MAX_CLK (2500000)
-
#ifndef NS9750_ETH_PHY_ADDRESS
# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
#endif /* NETARM_ETH_PHY_ADDRESS */
projects / project / bcm63xx / u-boot.git / commitdiff