ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field

dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit
field in the Channel Control Register (see Table 3-21 of the DMA-330
Technical Reference Manual) and should be programmed as such.

Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com>

Signed-off-by: Javi Merino <javi.merino@arm.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
index 575fa8186ca0fcb47ce864ff564f13a69bed3660..c1821385abfacbcc1532a25ee1bd2b0307173c09 100644 (file)
--- a/arch/arm/include/asm/hardware/pl330.h
+++ b/arch/arm/include/asm/hardware/pl330.h
@@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
        DCCTRL1, /* Bufferable only */
        DCCTRL2, /* Cacheable, but do not allocate */
        DCCTRL3, /* Cacheable and bufferable, but do not allocate */
-       DINVALID1 = 8,
+       DINVALID1,              /* AWCACHE = 0x1000 */
        DINVALID2,
        DCCTRL6, /* Cacheable write-through, allocate on writes only */
        DCCTRL7, /* Cacheable write-back, allocate on writes only */