drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq

[WHY] dc sw clock implementation of navi10 and raven are not exact the
same. dcccg, dchub reference clock initialization is done after dc calls
vbios dispcontroller_init table. for raven family, before
dispcontroller_init is called by dc, the ref clk values are referred
by sw clock implementation and program asic register using wrong
values. this causes dchub pstate error. This need provide valid ref
clk values. for navi10, since dispcontroller_init is not called,
dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will
hit aeert. this need remove hubbub2_get_dchub_ref_freq from this
location and move to dcn20_init_hw.

[HOW] for all asic, initialize dccg, dchub ref clk with data from
vbios firmware table by default. for raven asic family, use these data
from vbios, for asic which support sw dccg component, like navi10,
read ref clk by sw dccg functions and update the ref clk.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 48dfb305a0b0999bd3681ec129fde81866b72cb5..51a78283a86da510837ce3ab3b6d3ae6bc1801bd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -175,32 +175,22 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
        if (res_pool != NULL) {
                struct dc_firmware_info fw_info = { { 0 } };
 
-               if (dc->ctx->dc_bios->funcs->get_firmware_info(
-                               dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
-                               res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
-
-                               if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-                                       // On FPGA these dividers are currently not configured by GDB
-                                       res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                       res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                               } else if (res_pool->dccg && res_pool->hubbub) {
-                                       // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error
-                                       // as this value must be known for DCHUB programming
-                                       (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
-                                                       fw_info.pll_info.crystal_frequency,
-                                                       &res_pool->ref_clocks.dccg_ref_clock_inKhz);
-
-                                       // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error
-                                       (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
-                                                       res_pool->ref_clocks.dccg_ref_clock_inKhz,
-                                                       &res_pool->ref_clocks.dchub_ref_clock_inKhz);
-                               } else {
-                                       // Not all ASICs have DCCG sw component
-                                       res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                       res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                               }
-                       } else
-                               ASSERT_CRITICAL(false);
+               if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
+                               &fw_info) == BP_RESULT_OK) {
+                       res_pool->ref_clocks.xtalin_clock_inKhz =
+                               fw_info.pll_info.crystal_frequency;
+                       /* initialize with firmware data first, no all
+                        * ASIC have DCCG SW component. FPGA or
+                        * simulation need initialization of
+                        * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
+                        * with xtalin_clock_inKhz
+                        */
+                       res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                       res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                               res_pool->ref_clocks.xtalin_clock_inKhz;
+               } else
+                       ASSERT_CRITICAL(false);
        }
 
        return res_pool;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6925d25d24573cfc96297b4584b3ca2d5f098526..0b84a322b8a2c01af95de8aad35765338e9e5d28 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -523,6 +523,7 @@ static void dcn20_init_hw(struct dc *dc)
        struct dc_bios *dcb = dc->ctx->dc_bios;
        struct resource_pool *res_pool = dc->res_pool;
        struct dc_state  *context = dc->current_state;
+       struct dc_firmware_info fw_info = { { 0 } };
 
        if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
                dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -546,6 +547,30 @@ static void dcn20_init_hw(struct dc *dc)
        } else {
                if (!dcb->funcs->is_accelerated_mode(dcb)) {
                        bios_golden_init(dc);
+                       if (dc->ctx->dc_bios->funcs->get_firmware_info(
+                                       dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+                               res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
+
+                               if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+                                       if (res_pool->dccg && res_pool->hubbub) {
+
+                                               (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+                                                               fw_info.pll_info.crystal_frequency,
+                                                               &res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+                                               (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+                                                               res_pool->ref_clocks.dccg_ref_clock_inKhz,
+                                                               &res_pool->ref_clocks.dchub_ref_clock_inKhz);
+                                       } else {
+                                               // Not all ASICs have DCCG sw component
+                                               res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                                                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                                               res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                                                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                                       }
+                               }
+                       } else
+                               ASSERT_CRITICAL(false);
                        disable_vga(dc->hwseq);
                }