config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
- depends on EXPERIMENTAL && REALVIEW_MPCORE
+ depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
config LOCAL_TIMERS
bool "Use local timer interrupts"
- depends on SMP && REALVIEW_MPCORE
+ depends on SMP && REALVIEW_EB_ARM11MP
default y
help
Enable support for local timers on SMP platforms, rather then the
help
Include support for the ARM(R) RealView Emulation Baseboard platform.
-config REALVIEW_MPCORE
- bool "Support MPcore tile"
+config REALVIEW_EB_ARM11MP
+ bool "Support ARM11MPCore tile"
depends on MACH_REALVIEW_EB
select CACHE_L2X0
help
- Enable support for the MPCore tile on the Realview platform.
- Since there are device address and interrupt differences, a
- kernel built with this option enabled is not compatible with
- other tiles.
+ Enable support for the ARM11MPCore tile on the Realview platform.
-config REALVIEW_MPCORE_REVB
- bool "Support MPcore RevB tile"
- depends on REALVIEW_MPCORE
+config REALVIEW_EB_ARM11MP_REVB
+ bool "Support ARM11MPCore RevB tile"
+ depends on REALVIEW_EB_ARM11MP
default n
help
- Enable support for the MPCore RevB tile on the Realview platform.
- Since there are device address differences, a
+ Enable support for the ARM11MPCore RevB tile on the Realview
+ platform. Since there are device address differences, a
kernel built with this option enabled is not compatible with
- other tiles.
+ other revisions of the ARM11MPCore tile.
endmenu
gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
gic_cpu_init(0, gic_cpu_base_addr);
-#ifndef CONFIG_REALVIEW_MPCORE_REVB
+#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
/* board GIC, secondary */
gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64);
gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE));
/*
* RealView EB + ARM11MPCore peripheral addresses
*/
-#ifdef CONFIG_REALVIEW_MPCORE_REVB
+#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
#define REALVIEW_EB11MP_TWD_BASE 0x10100700
#define NR_IRQS NR_IRQS_EB
#endif
-#if defined(CONFIG_REALVIEW_MPCORE) \
+#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
&& (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
#undef MAX_GIC_NR
#define MAX_GIC_NR NR_GIC_EB11MP
((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
== proc_type)
-#ifdef CONFIG_REALVIEW_MPCORE
+#ifdef CONFIG_REALVIEW_EB_ARM11MP
#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
#else
#define core_tile_eb11mp() 0