struct device *dev = &plat_dev->dev;
struct device_node *np = dev->of_node;
u32 signature_val;
+ dma_addr_t dma_mask;
int rc = 0;
new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
}
dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq);
+ if (!plat_dev->dev.dma_mask)
+ plat_dev->dev.dma_mask = &plat_dev->dev.coherent_dma_mask;
+
+ dma_mask = (dma_addr_t)(DMA_BIT_MASK(DMA_BIT_MASK_LEN));
+ while (dma_mask > 0x7fffffffUL) {
+ if (dma_supported(&plat_dev->dev, dma_mask)) {
+ rc = dma_set_coherent_mask(&plat_dev->dev, dma_mask);
+ if (!rc)
+ break;
+ }
+ dma_mask >>= 1;
+ }
+
+ if (rc) {
+ dev_err(dev, "Error: failed in dma_set_mask, mask=%par\n",
+ &dma_mask);
+ goto post_drvdata_err;
+ }
+
rc = cc_clk_on(new_drvdata);
if (rc)
goto post_drvdata_err;
- if (!dev->dma_mask)
- dev->dma_mask = &dev->coherent_dma_mask;
-
- if (!dev->coherent_dma_mask)
- dev->coherent_dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
/* Verify correct mapping */
signature_val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE));