clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based

Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be
more obvious it is clk_hw based.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 48bad87f0aa0da31aa3885d9783daee613075a80..88510f3e77f53c6d5634c6d4e7842bf63f701576 100644 (file)
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -94,16 +94,16 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
        clks[IMX7ULP_CLK_SPLL]          = imx_clk_hw_pllv4("spll",  "spll_pre_div", base + 0x600);
 
        /* APLL PFDs */
-       clks[IMX7ULP_CLK_APLL_PFD0]     = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
-       clks[IMX7ULP_CLK_APLL_PFD1]     = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
-       clks[IMX7ULP_CLK_APLL_PFD2]     = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
-       clks[IMX7ULP_CLK_APLL_PFD3]     = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
+       clks[IMX7ULP_CLK_APLL_PFD0]     = imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
+       clks[IMX7ULP_CLK_APLL_PFD1]     = imx_clk_hw_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
+       clks[IMX7ULP_CLK_APLL_PFD2]     = imx_clk_hw_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
+       clks[IMX7ULP_CLK_APLL_PFD3]     = imx_clk_hw_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
 
        /* SPLL PFDs */
-       clks[IMX7ULP_CLK_SPLL_PFD0]     = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
-       clks[IMX7ULP_CLK_SPLL_PFD1]     = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
-       clks[IMX7ULP_CLK_SPLL_PFD2]     = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
-       clks[IMX7ULP_CLK_SPLL_PFD3]     = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
+       clks[IMX7ULP_CLK_SPLL_PFD0]     = imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
+       clks[IMX7ULP_CLK_SPLL_PFD1]     = imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
+       clks[IMX7ULP_CLK_SPLL_PFD2]     = imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
+       clks[IMX7ULP_CLK_SPLL_PFD3]     = imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
 
        /* PLL Mux */
        clks[IMX7ULP_CLK_APLL_PFD_SEL]  = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);

diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
index a03bbed662c6bccd94f13497298a0d474e772705..de93ce73101b9e8b180d12ff23b93c13ab10bf2c 100644 (file)
--- a/drivers/clk/imx/clk-pfdv2.c
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -166,7 +166,7 @@ static const struct clk_ops clk_pfdv2_ops = {
        .is_enabled     = clk_pfdv2_is_enabled,
 };
 
-struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
                             void __iomem *reg, u8 idx)
 {
        struct clk_init_data init;

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index ee71aa9ee76d6d0e14109473256853b1a1d375b8..c7285dbc6f53d2dee081878f04289f84a8a27367 100644 (file)
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -200,7 +200,7 @@ struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
                void __iomem *reg, u8 idx);
 
-struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
                             void __iomem *reg, u8 idx);
 
 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,