This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_map` array.
Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
CSS_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
+#define CSS_MAP_NSRAM MAP_REGION_FLAT( \
+ NSRAM_BASE, \
+ NSRAM_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
/* Platform ID address */
#define SSC_VERSION_OFFSET 0x040
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
CSS_MAP_DEVICE,
+#if CSS_USE_SCMI_DRIVER
+ /*
+ * The SCMI payload area is currently in the Non Secure SRAM. This is
+ * a potential security risk but this will be resolved once SCP
+ * completely replaces SCPI with SCMI as the only communication
+ * protocol.
+ */
+ CSS_MAP_NSRAM,
+#endif
SOC_CSS_MAP_DEVICE,
{0}
};
#endif
#ifdef IMAGE_BL31
-# define PLAT_ARM_MMAP_ENTRIES 5
-# define MAX_XLAT_TABLES 2
+# if CSS_USE_SCMI_DRIVER
+# define PLAT_ARM_MMAP_ENTRIES 6
+# define MAX_XLAT_TABLES 3
+# else
+# define PLAT_ARM_MMAP_ENTRIES 5
+# define MAX_XLAT_TABLES 2
+# endif
#endif
#ifdef IMAGE_BL32
return (((mpidr) & 0x100) ? JUNO_CLUSTER1_CORE_COUNT :\
JUNO_CLUSTER0_CORE_COUNT);
}
+
+/*
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ */
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
+ 2, 3, 4, 5, 0, 1 };