pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
+ pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
- pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+ pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
PFUZE100_SW1ABSTBY = 0x21,
PFUZE100_SW1ABOFF = 0x22,
PFUZE100_SW1ABMODE = 0x23,
- PUZE_100_SW1ABCONF = 0x24,
+ PFUZE100_SW1ABCONF = 0x24,
PFUZE100_SW1CVOL = 0x2e,
PFUZE100_SW1CSTBY = 0x2f,
PFUZE100_SW1COFF = 0x30,