drm/i915: add gen6+ registers to i915_swizzle_info

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 681cbe4e6e2d02bf934a637f761532e8d03102c0..4ebca6d0494fead443a96b3241637b13da8795e9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1422,6 +1422,19 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
                           I915_READ16(C0DRB3));
                seq_printf(m, "C1DRB3 = 0x%04x\n",
                           I915_READ16(C1DRB3));
+       } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
+               seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
+                          I915_READ(MAD_DIMM_C0));
+               seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
+                          I915_READ(MAD_DIMM_C1));
+               seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
+                          I915_READ(MAD_DIMM_C2));
+               seq_printf(m, "TILECTL = 0x%08x\n",
+                          I915_READ(TILECTL));
+               seq_printf(m, "ARB_MODE = 0x%08x\n",
+                          I915_READ(ARB_MODE));
+               seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
+                          I915_READ(DISP_ARB_CTL));
        }
        mutex_unlock(&dev->struct_mutex);