drm/amd: the data retured from PRT is expected to be 0
authorJack Xiao <Jack.Xiao@amd.com>
Mon, 20 May 2019 04:16:19 +0000 (12:16 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 23:59:32 +0000 (18:59 -0500)
The dummy page for returning from PRT resides inside system memory,
need set system flag bit in VM_L2_CNTL.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

index 231c77aed01b470ca03e6f0dc3669e21ef227990..b7de60a156232c182793cd19d45c8c0232308e85 100644 (file)
@@ -135,7 +135,8 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
        tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
-
+       tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
+                           ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
        /* XXX for emulation, Refer to closed source code.*/
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
                            L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
index f65b9c827970d64a7be7b1509476250c5b5b8f47..37a1a318ae63b5fc9919a81b9e43dd5465a8d972 100644 (file)
@@ -121,6 +121,8 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
        tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
        tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
        tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+       tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
+                           ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
        /* XXX for emulation, Refer to closed source code.*/
        tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
                            0);