drm/i915: Repack fence tiling mode and stride into a single integer

In the previous commit, we moved the obj->tiling_mode out of a bitfield
and into its own integer so that we could safely use READ_ONCE(). Let us
now repair some of that damage by sharing the tiling_mode with its
companion, the fence stride.

v2: New magic

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470388464-28458-18-git-send-email-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1faea382dfeb08cb206feb3879dca4729d762034..0620a84d00ca0059a531ef8ca4477f9a09b63537 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -101,7 +101,7 @@ static char get_pin_flag(struct drm_i915_gem_object *obj)
 
 static char get_tiling_flag(struct drm_i915_gem_object *obj)
 {
-       switch (obj->tiling_mode) {
+       switch (i915_gem_object_get_tiling(obj)) {
        default:
        case I915_TILING_NONE: return ' ';
        case I915_TILING_X: return 'X';

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f18d8761305c7ad1af1a4d2f7118ba71c192659b..feec00f769e115628d453b5ca226cc717e3d62f9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2214,13 +2214,11 @@ struct drm_i915_gem_object {
 
        atomic_t frontbuffer_bits;
 
-       /**
-        * Current tiling mode for the object.
-        */
-       unsigned int tiling_mode;
-
        /** Current tiling stride for the object, if it's tiled. */
-       uint32_t stride;
+       unsigned int tiling_and_stride;
+#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
+#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
+#define STRIDE_MASK (~TILING_MASK)
 
        unsigned int has_wc_mmap;
        /** Count of VMA actually bound by this object */
@@ -2359,6 +2357,24 @@ i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
        return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
 }
 
+static inline unsigned int
+i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
+{
+       return obj->tiling_and_stride & TILING_MASK;
+}
+
+static inline bool
+i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
+{
+       return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
+}
+
+static inline unsigned int
+i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
+{
+       return obj->tiling_and_stride & STRIDE_MASK;
+}
+
 /*
  * Optimised SGL iterator for GEM objects
  */
@@ -3457,7 +3473,7 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
        struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 
        return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
-               obj->tiling_mode != I915_TILING_NONE;
+               i915_gem_object_is_tiled(obj);
 }
 
 /* i915_debugfs.c */

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4e66045439b878bf0fef333833ef949995edc12c..7a00678ae72918a6370daa33bf1f44f965ef61d0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1042,7 +1042,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915,
        int ret;
        bool hit_slow_path = false;
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                return -EFAULT;
 
        ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
@@ -1671,7 +1671,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 
        /* Use a partial view if the object is bigger than the aperture. */
        if (obj->base.size >= ggtt->mappable_end &&
-           obj->tiling_mode == I915_TILING_NONE) {
+           !i915_gem_object_is_tiled(obj)) {
                static const unsigned int chunk_size = 256; // 1 MiB
 
                memset(&view, 0, sizeof(view));
@@ -2189,7 +2189,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
        if (i915_gem_object_needs_bit17_swizzle(obj))
                i915_gem_object_do_bit_17_swizzle(obj);
 
-       if (obj->tiling_mode != I915_TILING_NONE &&
+       if (i915_gem_object_is_tiled(obj) &&
            dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
                i915_gem_object_pin_pages(obj);
 
@@ -2938,10 +2938,12 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
 
        size = max(size, vma->size);
        if (flags & PIN_MAPPABLE)
-               size = i915_gem_get_ggtt_size(dev_priv, size, obj->tiling_mode);
+               size = i915_gem_get_ggtt_size(dev_priv, size,
+                                             i915_gem_object_get_tiling(obj));
 
        min_alignment =
-               i915_gem_get_ggtt_alignment(dev_priv, size, obj->tiling_mode,
+               i915_gem_get_ggtt_alignment(dev_priv, size,
+                                           i915_gem_object_get_tiling(obj),
                                            flags & PIN_MAPPABLE);
        if (alignment == 0)
                alignment = min_alignment;
@@ -3637,10 +3639,10 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
 
        fence_size = i915_gem_get_ggtt_size(dev_priv,
                                            obj->base.size,
-                                           obj->tiling_mode);
+                                           i915_gem_object_get_tiling(obj));
        fence_alignment = i915_gem_get_ggtt_alignment(dev_priv,
                                                      obj->base.size,
-                                                     obj->tiling_mode,
+                                                     i915_gem_object_get_tiling(obj),
                                                      true);
 
        fenceable = (vma->node.size == fence_size &&
@@ -3884,7 +3886,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
        }
 
        if (obj->pages &&
-           obj->tiling_mode != I915_TILING_NONE &&
+           i915_gem_object_is_tiled(obj) &&
            dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
                if (obj->madv == I915_MADV_WILLNEED)
                        i915_gem_object_unpin_pages(obj);
@@ -4054,7 +4056,7 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
 
        if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
            dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
-           obj->tiling_mode != I915_TILING_NONE)
+           i915_gem_object_is_tiled(obj))
                i915_gem_object_unpin_pages(obj);
 
        if (WARN_ON(obj->pages_pin_count))

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 71834741bd87e08f5ab4ac309b43c37160f89667..c494b79ded20e4b0618a7ca1dcdf6588a1deb3c1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -803,7 +803,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
                        entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
                need_fence =
                        entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
-                       obj->tiling_mode != I915_TILING_NONE;
+                       i915_gem_object_is_tiled(obj);
                need_mappable = need_fence || need_reloc_mappable(vma);
 
                if (entry->flags & EXEC_OBJECT_PINNED)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 3b462da612cabd206137e868eb08c5d3ed99c141..9e8173fe2a09a04e3c9616e8a5532ad043b74ef7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -86,20 +86,22 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 
        if (obj) {
                u32 size = i915_gem_obj_ggtt_size(obj);
+               unsigned int tiling = i915_gem_object_get_tiling(obj);
+               unsigned int stride = i915_gem_object_get_stride(obj);
                uint64_t val;
 
                /* Adjust fence size to match tiled area */
-               if (obj->tiling_mode != I915_TILING_NONE) {
-                       uint32_t row_size = obj->stride *
-                               (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
+               if (tiling != I915_TILING_NONE) {
+                       uint32_t row_size = stride *
+                               (tiling == I915_TILING_Y ? 32 : 8);
                        size = (size / row_size) * row_size;
                }
 
                val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
                                 0xfffff000) << 32;
                val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
-               val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
-               if (obj->tiling_mode == I915_TILING_Y)
+               val |= (uint64_t)((stride / 128) - 1) << fence_pitch_shift;
+               if (tiling == I915_TILING_Y)
                        val |= 1 << I965_FENCE_TILING_Y_SHIFT;
                val |= I965_FENCE_REG_VALID;
 
@@ -122,6 +124,8 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
 
        if (obj) {
                u32 size = i915_gem_obj_ggtt_size(obj);
+               unsigned int tiling = i915_gem_object_get_tiling(obj);
+               unsigned int stride = i915_gem_object_get_stride(obj);
                int pitch_val;
                int tile_width;
 
@@ -131,17 +135,17 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
                     "object 0x%08llx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
                     i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
 
-               if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
+               if (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
                        tile_width = 128;
                else
                        tile_width = 512;
 
                /* Note: pitch better be a power of two tile widths */
-               pitch_val = obj->stride / tile_width;
+               pitch_val = stride / tile_width;
                pitch_val = ffs(pitch_val) - 1;
 
                val = i915_gem_obj_ggtt_offset(obj);
-               if (obj->tiling_mode == I915_TILING_Y)
+               if (tiling == I915_TILING_Y)
                        val |= 1 << I830_FENCE_TILING_Y_SHIFT;
                val |= I915_FENCE_SIZE_BITS(size);
                val |= pitch_val << I830_FENCE_PITCH_SHIFT;
@@ -161,6 +165,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
 
        if (obj) {
                u32 size = i915_gem_obj_ggtt_size(obj);
+               unsigned int tiling = i915_gem_object_get_tiling(obj);
+               unsigned int stride = i915_gem_object_get_stride(obj);
                uint32_t pitch_val;
 
                WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
@@ -169,11 +175,11 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
                     "object 0x%08llx not 512K or pot-size 0x%08x aligned\n",
                     i915_gem_obj_ggtt_offset(obj), size);
 
-               pitch_val = obj->stride / 128;
+               pitch_val = stride / 128;
                pitch_val = ffs(pitch_val) - 1;
 
                val = i915_gem_obj_ggtt_offset(obj);
-               if (obj->tiling_mode == I915_TILING_Y)
+               if (tiling == I915_TILING_Y)
                        val |= 1 << I830_FENCE_TILING_Y_SHIFT;
                val |= I830_FENCE_SIZE_BITS(size);
                val |= pitch_val << I830_FENCE_PITCH_SHIFT;
@@ -201,9 +207,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg,
        if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
                mb();
 
-       WARN(obj && (!obj->stride || !obj->tiling_mode),
+       WARN(obj &&
+            (!i915_gem_object_get_stride(obj) ||
+             !i915_gem_object_get_tiling(obj)),
             "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
-            obj->stride, obj->tiling_mode);
+            i915_gem_object_get_stride(obj),
+            i915_gem_object_get_tiling(obj));
 
        if (IS_GEN2(dev))
                i830_write_fence_reg(dev, reg, obj);
@@ -248,7 +257,7 @@ static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
 
 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
 {
-       if (obj->tiling_mode)
+       if (i915_gem_object_is_tiled(obj))
                i915_gem_release_mmap(obj);
 
        /* As we do not have an associated fence register, we will force
@@ -361,7 +370,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
 {
        struct drm_device *dev = obj->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
-       bool enable = obj->tiling_mode != I915_TILING_NONE;
+       bool enable = i915_gem_object_is_tiled(obj);
        struct drm_i915_fence_reg *reg;
        int ret;
 
@@ -477,7 +486,7 @@ void i915_gem_restore_fences(struct drm_device *dev)
                 */
                if (reg->obj) {
                        i915_gem_object_update_fence(reg->obj, reg,
-                                                    reg->obj->tiling_mode);
+                                                    i915_gem_object_get_tiling(reg->obj));
                } else {
                        i915_gem_write_fence(dev, i, NULL);
                }

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 6817f69947d9c7aa0fa6842df203205e59c096dc..f4b984de83b537a4a0257e79a43abfb71a017a56 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -170,6 +170,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
        struct drm_i915_gem_object *obj;
        int ret = 0;
 
+       /* Make sure we don't cross-contaminate obj->tiling_and_stride */
+       BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
+
        obj = i915_gem_object_lookup(file, args->handle);
        if (!obj)
                return -ENOENT;
@@ -217,8 +220,8 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                }
        }
 
-       if (args->tiling_mode != obj->tiling_mode ||
-           args->stride != obj->stride) {
+       if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
+           args->stride != i915_gem_object_get_stride(obj)) {
                /* We need to rebind the object if its current allocation
                 * no longer meets the alignment restrictions for its new
                 * tiling mode. Otherwise we can just leave it alone, but
@@ -241,7 +244,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                            dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
                                if (args->tiling_mode == I915_TILING_NONE)
                                        i915_gem_object_unpin_pages(obj);
-                               if (obj->tiling_mode == I915_TILING_NONE)
+                               if (!i915_gem_object_is_tiled(obj))
                                        i915_gem_object_pin_pages(obj);
                        }
 
@@ -250,16 +253,16 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                                                         &dev->struct_mutex) ||
                                obj->fence_reg != I915_FENCE_REG_NONE;
 
-                       obj->tiling_mode = args->tiling_mode;
-                       obj->stride = args->stride;
+                       obj->tiling_and_stride =
+                               args->stride | args->tiling_mode;
 
                        /* Force the fence to be reacquired for GTT access */
                        i915_gem_release_mmap(obj);
                }
        }
        /* we have to maintain this existing ABI... */
-       args->stride = obj->stride;
-       args->tiling_mode = obj->tiling_mode;
+       args->stride = i915_gem_object_get_stride(obj);
+       args->tiling_mode = i915_gem_object_get_tiling(obj);
 
        /* Try to preallocate memory required to save swizzling on put-pages */
        if (i915_gem_object_needs_bit17_swizzle(obj)) {
@@ -306,7 +309,7 @@ i915_gem_get_tiling(struct drm_device *dev, void *data,
        if (!obj)
                return -ENOENT;
 
-       args->tiling_mode = READ_ONCE(obj->tiling_mode);
+       args->tiling_mode = READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
        switch (args->tiling_mode) {
        case I915_TILING_X:
                args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index cc28ad429dd8440327309b2bc734d09940846507..eecb87063c88f47e9cbeee356b362858b04702b7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -781,7 +781,7 @@ static void capture_bo(struct drm_i915_error_buffer *err,
        err->pinned = 0;
        if (i915_gem_obj_is_pinned(obj))
                err->pinned = 1;
-       err->tiling = obj->tiling_mode;
+       err->tiling = i915_gem_object_get_tiling(obj);
        err->dirty = obj->dirty;
        err->purgeable = obj->madv != I915_MADV_WILLNEED;
        err->userptr = obj->userptr.mm != NULL;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9068676943bfbd3f103d32b14ab3698a13ce654f..9cbf5431c1e34dcf41865161a9e880fa60a809af 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2466,9 +2466,8 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
                return false;
        }
 
-       obj->tiling_mode = plane_config->tiling;
-       if (obj->tiling_mode == I915_TILING_X)
-               obj->stride = fb->pitches[0];
+       if (plane_config->tiling == I915_TILING_X)
+               obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
 
        mode_cmd.pixel_format = fb->pixel_format;
        mode_cmd.width = fb->width;
@@ -2594,7 +2593,7 @@ valid_fb:
        intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
 
        obj = intel_fb_obj(fb);
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                dev_priv->preserve_bios_swizzle = true;
 
        drm_framebuffer_reference(fb);
@@ -2672,8 +2671,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
                BUG();
        }
 
-       if (INTEL_INFO(dev)->gen >= 4 &&
-           obj->tiling_mode != I915_TILING_NONE)
+       if (INTEL_INFO(dev)->gen >= 4 && i915_gem_object_is_tiled(obj))
                dspcntr |= DISPPLANE_TILED;
 
        if (IS_G4X(dev))
@@ -2782,7 +2780,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
                BUG();
        }
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                dspcntr |= DISPPLANE_TILED;
 
        if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
@@ -11200,7 +11198,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
                        MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
        intel_ring_emit(ring, fb->pitches[0]);
        intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
-                       obj->tiling_mode);
+                       i915_gem_object_get_tiling(obj));
 
        /* XXX Enabling the panel-fitter across page-flip is so far
         * untested on non-native modes, so ignore it for now.
@@ -11232,7 +11230,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
 
        intel_ring_emit(ring, MI_DISPLAY_FLIP |
                        MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-       intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+       intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj));
        intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
 
        /* Contrary to the suggestions in the documentation,
@@ -11335,7 +11333,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
        }
 
        intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
-       intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+       intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj));
        intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
        intel_ring_emit(ring, (MI_NOOP));
 
@@ -11442,7 +11440,7 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
 
        dspcntr = I915_READ(reg);
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                dspcntr |= DISPPLANE_TILED;
        else
                dspcntr &= ~DISPPLANE_TILED;
@@ -11670,7 +11668,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
                engine = &dev_priv->engine[BCS];
-               if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
+               if (i915_gem_object_get_tiling(obj) !=
+                   i915_gem_object_get_tiling(intel_fb_obj(work->old_fb)))
                        /* vlv: DISPLAY_FLIP fails to change tiling */
                        engine = NULL;
        } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -14932,15 +14931,15 @@ static int intel_framebuffer_init(struct drm_device *dev,
        if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
                /* Enforce that fb modifier and tiling mode match, but only for
                 * X-tiled. This is needed for FBC. */
-               if (!!(obj->tiling_mode == I915_TILING_X) !=
+               if (!!(i915_gem_object_get_tiling(obj) == I915_TILING_X) !=
                    !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
                        DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
                        return -EINVAL;
                }
        } else {
-               if (obj->tiling_mode == I915_TILING_X)
+               if (i915_gem_object_get_tiling(obj) == I915_TILING_X)
                        mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
-               else if (obj->tiling_mode == I915_TILING_Y) {
+               else if (i915_gem_object_get_tiling(obj) == I915_TILING_Y) {
                        DRM_DEBUG("No Y tiling for legacy addfb\n");
                        return -EINVAL;
                }
@@ -14984,9 +14983,10 @@ static int intel_framebuffer_init(struct drm_device *dev,
        }
 
        if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
-           mode_cmd->pitches[0] != obj->stride) {
+           mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
                DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
-                         mode_cmd->pitches[0], obj->stride);
+                         mode_cmd->pitches[0],
+                         i915_gem_object_get_stride(obj));
                return -EINVAL;
        }
 

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index d4be07615aa9835c51867216867efb25bdef03a1..85adc2b925947ab8d718597715fdaf0e2cc9563c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -741,7 +741,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
        cache->fb.pixel_format = fb->pixel_format;
        cache->fb.stride = fb->pitches[0];
        cache->fb.fence_reg = obj->fence_reg;
-       cache->fb.tiling_mode = obj->tiling_mode;
+       cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
 }
 
 static bool intel_fbc_can_activate(struct intel_crtc *crtc)

diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 413a2038e6d1506cddf714dbee682c70a2c787f9..90f3ab424e01ab6cd3f7dcf02869b189951b0f15 100644 (file)
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1129,7 +1129,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
        drm_modeset_lock_all(dev);
        mutex_lock(&dev->struct_mutex);
 
-       if (new_bo->tiling_mode) {
+       if (i915_gem_object_is_tiled(new_bo)) {
                DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
                ret = -EINVAL;
                goto out_unlock;

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eedcacef7d5c15eba24fa1effe1b7301eadb9487..aef0b105eb58bd8f04c9f60440583089bb82afbd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1585,7 +1585,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                obj = intel_fb_obj(enabled->primary->state->fb);
 
                /* self-refresh seems busted with untiled */
-               if (obj->tiling_mode == I915_TILING_NONE)
+               if (!i915_gem_object_is_tiled(obj))
                        enabled = NULL;
        }
 

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index e045295ef4af0fec04b67a89248807f0f1de80e5..9ed7ad32cffd25e21747fc7d075f3ad2d7abdac2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -431,7 +431,7 @@ vlv_update_plane(struct drm_plane *dplane,
         */
        sprctl |= SP_GAMMA_ENABLE;
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                sprctl |= SP_TILED;
 
        /* Sizes are 0 based */
@@ -468,7 +468,7 @@ vlv_update_plane(struct drm_plane *dplane,
        I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
        I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
        else
                I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
@@ -553,7 +553,7 @@ ivb_update_plane(struct drm_plane *plane,
         */
        sprctl |= SPRITE_GAMMA_ENABLE;
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                sprctl |= SPRITE_TILED;
 
        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -607,7 +607,7 @@ ivb_update_plane(struct drm_plane *plane,
         * register */
        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
-       else if (obj->tiling_mode != I915_TILING_NONE)
+       else if (i915_gem_object_is_tiled(obj))
                I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
        else
                I915_WRITE(SPRLINOFF(pipe), linear_offset);
@@ -694,7 +694,7 @@ ilk_update_plane(struct drm_plane *plane,
         */
        dvscntr |= DVS_GAMMA_ENABLE;
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                dvscntr |= DVS_TILED;
 
        if (IS_GEN6(dev))
@@ -737,7 +737,7 @@ ilk_update_plane(struct drm_plane *plane,
        I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
        I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-       if (obj->tiling_mode != I915_TILING_NONE)
+       if (i915_gem_object_is_tiled(obj))
                I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
        else
                I915_WRITE(DVSLINOFF(pipe), linear_offset);