lots of ifxmips fixes and features

SVN-Revision: 11673

diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c b/target/linux/ifxmips/files/arch/mips/ifxmips/board.c
index 0d932a21481a34613021f39b9a140058c72f69bc..e4ef45408fa5febe294689dd564ba6253847f771 100644 (file)
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/board.c
@@ -32,7 +32,6 @@
 #include <asm/io.h>
 #include <linux/etherdevice.h>
 #include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_mii0.h>
 
 #define MAX_BOARD_NAME_LEN             32
 #define MAX_IFXMIPS_DEVS               9
@@ -63,7 +62,8 @@ struct ifxmips_board {
 spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED;
 EXPORT_SYMBOL_GPL(ebu_lock);
 
-static struct ifxmips_mac ifxmips_mii_mac;
+static unsigned char ifxmips_mii_mac[6];
+static int ifxmips_brn = 0;
 
 static struct platform_device
 ifxmips_led =
@@ -86,7 +86,7 @@ ifxmips_mii =
        .id = 0,
        .name = "ifxmips_mii0",
        .dev = {
-               .platform_data = &ifxmips_mii_mac,
+               .platform_data = ifxmips_mii_mac,
        }
 };
 
@@ -172,9 +172,9 @@ ifxmips_set_mii0_mac(char *str)
                        goto out;
                if((i != 5) && (str[(3 * i) + 2] != ':'))
                        goto out;
-               ifxmips_mii_mac.mac[i] = simple_strtoul(&str[3 * i], NULL, 16);
+               ifxmips_mii_mac[i] = simple_strtoul(&str[3 * i], NULL, 16);
        }
-       if(is_valid_ether_addr(ifxmips_mii_mac.mac))
+       if(is_valid_ether_addr(ifxmips_mii_mac))
                cmdline_mac = 1;
 out:
        return 1;
@@ -257,7 +257,24 @@ static struct ifxmips_board boards[] =
        },
 };
 
-struct ifxmips_board* ifxmips_find_board(void)
+int
+ifxmips_find_brn_block(void){
+       unsigned char temp[0];
+       memcpy_fromio(temp, (void*)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8);
+       if(memcmp(temp, "BRN-BOOT", 8) == 0)
+               return 1;
+       else
+               return 0;
+}
+
+int
+ifxmips_has_brn_block(void)
+{
+       return ifxmips_brn;
+}
+
+struct ifxmips_board*
+ifxmips_find_board(void)
 {
        int i;
        if(!*board_name)
@@ -274,9 +291,10 @@ ifxmips_init_devices(void)
        struct ifxmips_board *board = ifxmips_find_board();
 
        chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID);
+       ifxmips_brn = ifxmips_find_brn_block();
 
        if(!cmdline_mac)
-               random_ether_addr(ifxmips_mii_mac.mac);
+               random_ether_addr(ifxmips_mii_mac);
 
        if(!board)
        {

diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
index c86b70cc04704beb0345f7fee6ba9f9558623af6..fc3658b71fbf5bbe918d3dd0d1cfeecd33b2a058 100644 (file)
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
@@ -31,46 +31,45 @@
 #include <linux/errno.h>
 #include <asm/ifxmips/ifxmips.h>
 
-#define FIX_FOR_36M_CRYSTAL             1
 #define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
 #define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
 
 #define BASIS_INPUT_CRYSTAL_USB         12000000
 
 #define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-#define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 
-#define CGU_PLL0_PHASE_DIVIDER_ENABLE   (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
-#define CGU_PLL0_BYPASS                 (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
-#define CGU_PLL0_SRC                    (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
-#define CGU_PLL0_CFG_DSMSEL             (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
-#define CGU_PLL0_CFG_FRAC_EN            (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
+
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
+#define CGU_PLL0_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
+#define CGU_PLL0_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
+#define CGU_PLL0_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
+#define CGU_PLL1_SRC                    (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
+#define CGU_PLL1_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
+#define CGU_PLL1_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
+#define CGU_PLL1_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
+#define CGU_PLL2_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
+#define CGU_SYS_FPI_SEL                 (1 << 6)
+#define CGU_SYS_DDR_SEL                 0x3
+#define CGU_PLL0_SRC                    (1 << 29)
+
 #define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
 #define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
 #define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
-#define CGU_PLL1_SRC                    (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
-#define CGU_PLL1_BYPASS                 (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
-#define CGU_PLL1_CFG_DSMSEL             (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
-#define CGU_PLL1_CFG_FRAC_EN            (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
 #define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
 #define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
 #define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
-#define CGU_PLL2_PHASE_DIVIDER_ENABLE   (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
-#define CGU_PLL2_BYPASS                 (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
 #define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
 #define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
 #define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
 #define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
-#define CGU_SYS_PPESEL                  GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
-#define CGU_SYS_FPI_SEL                 (*IFXMIPS_CGU_SYS & (1 << 6))
-#define CGU_SYS_CPU1SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
-#define CGU_SYS_CPU0SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
-#define CGU_SYS_DDR_SEL                 GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
 #define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
-#define CGU_IF_CLK_USBSEL               GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
-#define CGU_IF_CLK_MIISEL               GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
 
 static unsigned int cgu_get_pll0_fdiv(void);
+unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+
+#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
+
 
 static inline unsigned int
 get_input_clock(int pll)
@@ -78,7 +77,7 @@ get_input_clock(int pll)
        switch(pll)
        {
        case 0:
-               if(CGU_PLL0_SRC)
+               if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
                        return BASIS_INPUT_CRYSTAL_USB;
                else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
                        return BASIC_INPUT_CLOCK_FREQUENCY_1;
@@ -169,134 +168,18 @@ cgu_get_pll0_fosc(void)
                                CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 }
 
-static inline unsigned int
-cgu_get_pll0_fps(int phase)
-{
-       register unsigned int fps = cgu_get_pll0_fosc();
-
-       switch(phase)
-       {
-       case 1:
-               /*  1.25    */
-               fps = ((fps << 2) + 2) / 5;
-               break;
-       case 2:
-               /*  1.5     */
-               fps = ((fps << 1) + 1) / 3;
-               break;
-       }
-       return fps;
-}
-
 static unsigned int
 cgu_get_pll0_fdiv(void)
 {
        register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
-
        return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 }
 
-static inline unsigned int
-cgu_get_pll1_fosc(void)
-{
-       if(CGU_PLL1_BYPASS)
-               return get_input_clock(1);
-       else
-               return !CGU_PLL1_CFG_FRAC_EN
-                       ? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
-                       : dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
-}
-
-static inline unsigned int
-cgu_get_pll1_fps(void)
-{
-       register unsigned int fps = cgu_get_pll1_fosc();
-
-       return ((fps << 1) + 1) / 3;
-}
-
-static inline unsigned int
-cgu_get_pll1_fdiv(void)
-{
-       return cgu_get_pll1_fosc();
-}
-
-static inline unsigned int
-cgu_get_pll2_fosc(void)
-{
-       u64 res, clock = get_input_clock(2);
-
-       if ( CGU_PLL2_BYPASS )
-               return get_input_clock(2);
-
-       res = (CGU_PLL2_CFG_PLLN + 1) * clock;
-       do_div(res, CGU_PLL2_CFG_PLLM + 1);
-
-       return res;
-}
-
-static inline unsigned int
-cgu_get_pll2_fps(int phase)
-{
-       register unsigned int fps = cgu_get_pll2_fosc();
-
-       switch ( phase )
-       {
-       case 1:
-               /*  1.125   */
-               fps = ((fps << 2) + 2) / 5; break;
-       case 2:
-               /*  1.25    */
-               fps = ((fps << 3) + 4) / 9;
-       }
-
-       return fps;
-}
-
-static inline unsigned int
-cgu_get_pll2_fdiv(void)
-{
-       register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
-       return (cgu_get_pll2_fosc() + (div >> 1)) / div;
-}
-
-unsigned int
-cgu_get_mips_clock(int cpu)
-{
-       register unsigned int ret = cgu_get_pll0_fosc();
-       register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
-
-       if(cpusel == 0)
-               return ret;
-       else if(cpusel == 2)
-               ret <<= 1;
-
-       switch(CGU_SYS_DDR_SEL)
-       {
-       default:
-       case 0:
-               return (ret + 1) / 2;
-       case 1:
-               return (ret * 2 + 2) / 5;
-       case 2:
-               return (ret + 1) / 3;
-       case 3:
-               return (ret + 2) / 4;
-       }
-}
-
-unsigned int
-cgu_get_cpu_clock(void)
-{
-       return cgu_get_mips_clock(0);
-}
-
 unsigned int
 cgu_get_io_region_clock(void)
 {
        register unsigned int ret = cgu_get_pll0_fosc();
-
-       switch(CGU_SYS_DDR_SEL)
+       switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL)
        {
        default:
        case 0:
@@ -314,112 +197,16 @@ unsigned int
 cgu_get_fpi_bus_clock(int fpi)
 {
        register unsigned int ret = cgu_get_io_region_clock();
-
-       if((fpi == 2) && (CGU_SYS_FPI_SEL))
+       if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
                ret >>= 1;
-
        return ret;
 }
 
-unsigned int
-cgu_get_pp32_clock(void)
-{
-       switch(CGU_SYS_PPESEL)
-       {
-       default:
-       case 0:
-               return cgu_get_pll2_fps(1);
-       case 1:
-               return cgu_get_pll2_fps(2);
-       case 2:
-               return (cgu_get_pll2_fps(1) + 1) >> 1;
-       case 3:
-               return (cgu_get_pll2_fps(2) + 1) >> 1;
-       }
-}
-
-unsigned int
-cgu_get_ethernet_clock(int mii)
-{
-       switch(CGU_IF_CLK_MIISEL)
-       {
-       case 0:
-               return (cgu_get_pll2_fosc() + 3) / 12;
-       case 1:
-               return (cgu_get_pll2_fosc() + 3) / 6;
-       case 2:
-               return 50000000;
-       case 3:
-               return 25000000;
-       }
-       return 0;
-}
-
-unsigned int
-cgu_get_usb_clock(void)
-{
-       switch(CGU_IF_CLK_USBSEL)
-       {
-       case 0:
-               return (cgu_get_pll2_fosc() + 12) / 25;
-       case 1:
-               return 12000000;
-       case 2:
-               return 12000000 / 4;
-       case 3:
-               return 12000000;
-       }
-       return 0;
-}
-
-unsigned int
-cgu_get_clockout(int clkout)
-{
-       unsigned int fosc1 = cgu_get_pll1_fosc();
-       unsigned int fosc2 = cgu_get_pll2_fosc();
-
-       if(clkout > 3 || clkout < 0)
-               return 0;
-
-       switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
-       {
-       case 0: /*  32.768KHz   */
-       case 15:
-               return (fosc1 + 6000) / 12000;
-       case 1: /*  1.536MHz    */
-               return (fosc1 + 128) / 256;
-       case 2: /*  2.5MHz      */
-               return (fosc2 + 60) / 120;
-       case 3: /*  12MHz       */
-       case 5:
-       case 12:
-               return (fosc2 + 12) / 25;
-       case 4: /*  40MHz       */
-               return (cgu_get_pll2_fps(2) + 3) / 6;
-       case 6: /*  24MHz       */
-               return (cgu_get_pll2_fps(2) + 5) / 10;
-       case 7: /*  48MHz       */
-               return (cgu_get_pll2_fps(2) + 2) / 5;
-       case 8: /*  25MHz       */
-       case 14:
-               return (fosc2 + 6) / 12;
-       case 9: /*  50MHz       */
-       case 13:
-               return (fosc2 + 3) / 6;
-       case 10:/*  30MHz       */
-               return (fosc2 + 5) / 10;
-       case 11:/*  60MHz       */
-               return (fosc2 + 2) / 5;
-       }
-       return 0;
-}
-
 void cgu_setup_pci_clk(int external_clock)
 {
        //set clock to 33Mhz 
        ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
        ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
-       // internal or external clock
        if(external_clock)
        {
                ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
@@ -430,26 +217,10 @@ void cgu_setup_pci_clk(int external_clock)
        }
 }
 
-unsigned int
-ifxmips_get_ddr_hz(void)
-{
-       switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
-       {
-       case 0:
-               return CLOCK_167M;
-       case 1:
-               return CLOCK_133M;
-       case 2:
-               return CLOCK_111M;
-       }
-       return CLOCK_83M;
-}
-EXPORT_SYMBOL(ifxmips_get_ddr_hz);
-
 unsigned int
 ifxmips_get_cpu_hz(void)
 {
-       unsigned int ddr_clock = ifxmips_get_ddr_hz();
+       unsigned int ddr_clock = DDR_HZ;
        switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
        {
        case 0:
@@ -464,11 +235,9 @@ EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 unsigned int
 ifxmips_get_fpi_hz(void)
 {
-       unsigned int ddr_clock = ifxmips_get_ddr_hz();
+       unsigned int ddr_clock = DDR_HZ;
        if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
                return ddr_clock >> 1;
        return ddr_clock;
 }
 EXPORT_SYMBOL(ifxmips_get_fpi_hz);
-
-

diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
index cf64bda97644b5894c121eaf0cf24660c7aab008..eef514669837c9bf400e20d07a279be5c8481f84 100644 (file)
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
@@ -39,7 +39,6 @@
 #include <asm/semaphore.h>
 #include <asm/uaccess.h>
 #include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_ioctl.h>
 
 #define MAX_PORTS                      2
 #define PINS_PER_PORT          16

diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
index cbfcb75f0d82b7d8e336d08aed2d4f2c226d82e4..880febc62bc49a8edb0efe3a64f97d2f6f69b7c3 100644 (file)
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
@@ -18,6 +18,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/bootmem.h>
 #include <asm/bootinfo.h>
 #include <asm/ifxmips/ifxmips.h>
@@ -83,11 +84,13 @@ unsigned int *prom_get_cp1_base(void)
 {
        return prom_cp1_base;
 }
+EXPORT_SYMBOL(prom_get_cp1_base);
 
 unsigned int prom_get_cp1_size(void)
 {
        return prom_cp1_size;
 }
+EXPORT_SYMBOL(prom_get_cp1_size);
 
 void __init
 prom_init(void)

diff --git a/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c b/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
index 98359eb9fab395022efa17152484ed6608cfeea5..b3692e72a041b00b6176264bbbeca07cf1c3d95f 100644 (file)
--- a/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
+++ b/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/cfi.h>
 #include <asm/ifxmips/ifxmips.h>
+#include <asm/ifxmips/ifxmips_prom.h>
 #include <asm/ifxmips/ifxmips_ebu.h>
 #include <linux/magic.h>
 #include <linux/platform_device.h>
@@ -90,14 +91,14 @@ ifxmips_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_
 }
 
 static struct mtd_partition
-ifxmips_partitions[4] = {
+ifxmips_partitions[] = {
        {
-               name:"U-Boot",
+               name:"uboot",
                offset:0x00000000,
                size:0x00020000,
        },
        {
-               name:"U-Boot-Env",
+               name:"uboot_env",
                offset:0x00020000,
                size:0x00010000,
        },
@@ -111,6 +112,11 @@ ifxmips_partitions[4] = {
                offset:0x0,
                size:0x0,
        },
+       {
+               name:"board_config",
+               offset:0x0,
+               size:0x0,
+       },
 };
 
 int
@@ -121,6 +127,18 @@ find_uImage_size(unsigned long start_offset){
        return temp + 0x40;
 }
 
+int
+find_brn_block(unsigned long start_offset){
+       unsigned char temp[9];
+       ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 8);
+       temp[8] = '\0';
+       printk(KERN_INFO "data in brn block %s\n", temp);
+       if(memcmp(temp, "BRN-BOOT", 8) == 0)
+               return 1;
+       else
+               return 0;
+}
+
 int
 detect_squashfs_partition(unsigned long start_offset){
        unsigned long temp;
@@ -170,12 +188,19 @@ ifxmips_mtd_probe(struct platform_device *dev)
                uimage_size += 0x10000;
        }
 
+       parts = &ifxmips_partitions[0];
        ifxmips_partitions[2].size = uimage_size;
        ifxmips_partitions[3].offset = ifxmips_partitions[2].offset + ifxmips_partitions[2].size;
        ifxmips_partitions[3].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - ifxmips_partitions[3].offset;
-
-       parts = &ifxmips_partitions[0];
-       add_mtd_partitions(ifxmips_mtd, parts, 4);
+       if(ifxmips_has_brn_block())
+       {
+               ifxmips_partitions[3].size -= ifxmips_mtd->erasesize;
+               ifxmips_partitions[4].offset = ifxmips_mtd->size - ifxmips_mtd->erasesize;
+               ifxmips_partitions[4].size = ifxmips_mtd->erasesize;
+               add_mtd_partitions(ifxmips_mtd, parts, 5);
+       } else {
+               add_mtd_partitions(ifxmips_mtd, parts, 4);
+       }
 
        printk(KERN_INFO "ifxmips_mtd: added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20);
        return 0;

diff --git a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
index cc3b9d46a76a0f4003340d33510433cadc046a8c..fe7f25ec2a4eea3cadd17d9680f81353142d9c4a 100644 (file)
--- a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
+++ b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
@@ -36,10 +36,15 @@
 #include <linux/init.h>
 #include <asm/delay.h>
 #include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_mii0.h>
 #include <asm/ifxmips/ifxmips_dma.h>
 #include <asm/ifxmips/ifxmips_pmu.h>
 
+struct ifxmips_mii_priv {
+       struct net_device_stats stats;
+       struct dma_device_info *dma_device;
+       struct sk_buff *skb;
+};
+
 static struct net_device *ifxmips_mii0_dev;
 static unsigned char mac_addr[MAX_ADDR_LEN];
 
@@ -63,6 +68,7 @@ ifxmips_read_mdio(u32 phy_addr, u32 phy_reg)
                ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
                ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
 
+       while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
        ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
        while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
        val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
@@ -343,10 +349,10 @@ static int
 ifxmips_mii_probe(struct platform_device *dev)
 {
        int result = 0;
-       struct ifxmips_mac *mac = (struct ifxmips_mac*)dev->dev.platform_data;
+       unsigned char *mac = (unsigned char*)dev->dev.platform_data;
        ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
        ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
-       memcpy(mac_addr, mac->mac, 6);
+       memcpy(mac_addr, mac, 6);
        strcpy(ifxmips_mii0_dev->name, "eth%d");
        ifxmips_mii_chip_init(REV_MII_MODE);
        result = register_netdev(ifxmips_mii0_dev);

diff --git a/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c b/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
index 17d933c20b18357b3b399506e8d7e3d60471236c..2dc8917fe1ea9dd627c7f10f24f37c1d31978eb0 100644 (file)
--- a/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
+++ b/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
@@ -48,7 +48,6 @@
 #include <asm/bitops.h>
 #include <asm/ifxmips/ifxmips.h>
 #include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifxmips_serial.h>
 
 #define PORT_IFXMIPSASC  111
 
@@ -161,7 +160,7 @@ ifxmipsasc_tx_chars(struct uart_port *port)
        }
 
        while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
-                               >> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
+                               >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL)
        {
                if(port->x_char)
                {
@@ -248,8 +247,8 @@ ifxmipsasc_startup(struct uart_port *port)
        ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
        ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
        ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
-       ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
-       ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
+       ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
+       ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
        wmb ();
        ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
 
@@ -399,7 +398,7 @@ ifxmipsasc_type(struct uart_port *port)
 {
        if(port->type == PORT_IFXMIPSASC)
        {
-               if(port->membase == IFXMIPS_ASC_BASE_ADDR)
+               if(port->membase == (void*)IFXMIPS_ASC_BASE_ADDR)
                        return "asc0";
                else
                        return "asc1";
@@ -501,7 +500,7 @@ ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
                do {
                        fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
                                        >> ASCFSTAT_TXFFLOFF;
-               } while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
+               } while(fifocnt == TXFIFO_FULL);
 
                if(s[i] == '\0')
                        break;
@@ -512,7 +511,7 @@ ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
                        do {
                                fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
                                        >> ASCFSTAT_TXFFLOFF;
-                       } while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
+                       } while(fifocnt == TXFIFO_FULL);
                }
                ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
        }

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
index 1c6c614329ae2d5fa91b97f5117211a6137c3ab2..8389611895fa8adf013716c2f7274fa109d78aaf 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
@@ -15,7 +15,6 @@
  *
  *   Copyright (C) 2005 infineon
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
  */
 #ifndef _IFXMIPS_H__
 #define _IFXMIPS_H__
@@ -71,8 +70,41 @@
 #define ASCOPT_STOPB                   0x8
 #define ASCOPT_PARODD                  0x0
 #define ASCOPT_CREAD                   0x20
-#define ASCFSTAT_TXFFLMASK             0x3F00
-#define ASCFSTAT_TXFFLOFF              8
+#define TXFIFO_FL                              1
+#define RXFIFO_FL                              1
+#define TXFIFO_FULL                            16
+#define ASCCLC_RMCMASK                 0x0000FF00
+#define ASCCLC_RMCOFFSET               8
+#define ASCCON_M_8ASYNC                        0x0
+#define ASCCON_M_7ASYNC                        0x2
+#define ASCCON_ODD                             0x00000020
+#define ASCCON_STP                             0x00000080
+#define ASCCON_BRS                             0x00000100
+#define ASCCON_FDE                             0x00000200
+#define ASCCON_R                               0x00008000
+#define ASCCON_FEN                             0x00020000
+#define ASCCON_ROEN                            0x00080000
+#define ASCCON_TOEN                            0x00100000
+#define ASCSTATE_PE                            0x00010000
+#define ASCSTATE_FE                            0x00020000
+#define ASCSTATE_ROE                   0x00080000
+#define ASCSTATE_ANY                   (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
+#define ASCWHBSTATE_CLRREN             0x00000001
+#define ASCWHBSTATE_SETREN             0x00000002
+#define ASCWHBSTATE_CLRPE              0x00000004
+#define ASCWHBSTATE_CLRFE              0x00000008
+#define ASCWHBSTATE_CLRROE             0x00000020
+#define ASCTXFCON_TXFEN                        0x0001
+#define ASCTXFCON_TXFFLU               0x0002
+#define ASCTXFCON_TXFITLMASK    0x3F00
+#define ASCTXFCON_TXFITLOFF     8
+#define ASCRXFCON_RXFEN         0x0001
+#define ASCRXFCON_RXFFLU        0x0002
+#define ASCRXFCON_RXFITLMASK    0x3F00
+#define ASCRXFCON_RXFITLOFF     8
+#define ASCFSTAT_RXFFLMASK      0x003F
+#define ASCFSTAT_TXFFLMASK      0x3F00
+#define ASCFSTAT_TXFFLOFF       8
 
 
 
@@ -334,7 +366,7 @@
 #define IFXMIPS_SSC_IRN                        ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
 #define IFXMIPS_SSC_SFCON              ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
 #define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
-#define IFXMIPS_SSC_STATE      ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
+#define IFXMIPS_SSC_STATE              ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
 #define IFXMIPS_SSC_WHBSTATE   ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
 #define IFXMIPS_SSC_FSTAT              ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
 #define IFXMIPS_SSC_ID                 ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
@@ -472,7 +504,7 @@
 #define IFXMIPS_MPS_AD0ENR             ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
 #define IFXMIPS_MPS_AD1ENR             ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
 
-#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)   (((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))
 #define IFXMIPS_MPS_CHIPID_VERSION_SET(value)  (((( 1 << 4) - 1) & (value)) << 28)
 #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)  (((value) >> 12) & ((1 << 16) - 1))
 #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)  (((( 1 << 16) - 1) & (value)) << 12)

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h
index 31ddb53bb26d0fc05c7770210dd2f820f31944cf..899bbbca3e0d6285984bbf6a5398cf2b8881b615 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h
@@ -1,15 +1,29 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ */
 #ifndef _IFXMIPS_CGU_H__
 #define _IFXMIPS_CGU_H__
-u32 cgu_get_mips_clock(int cpu);
-u32 cgu_get_cpu_clock(void);
-u32 cgu_get_io_region_clock(void);
-u32 cgu_get_fpi_bus_clock(int fpi);
-u32 cgu_get_pp32_clock(void);
-u32 cgu_get_ethernet_clock(int mii);
-u32 cgu_get_usb_clock(void);
-u32 cgu_get_clockout(int clkout);
+
+unsigned int cgu_get_mips_clock(int cpu);
+unsigned int cgu_get_io_region_clock(void);
+unsigned int cgu_get_fpi_bus_clock(int fpi);
 void cgu_setup_pci_clk(int internal_clock);
-u32 ifxmips_get_ddr_hz(void);
-u32 ifxmips_get_cpu_hz(void);
-u32 ifxmips_get_fpi_hz(void);
+unsigned int ifxmips_get_ddr_hz(void);
+unsigned int ifxmips_get_fpi_hz(void);
+unsigned int ifxmips_get_cpu_hz(void);
+
 #endif

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h
index c9dc6e20b6cd16561d61acb789a0f43d45d223f2..237db01ec43da9b6d3dec33fdb983c3a2b112596 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h
@@ -12,9 +12,7 @@
  *   You should have received a copy of the GNU General Public License
  *   along with this program; if not, write to the Free Software
  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
  */
 #ifndef _IFXMIPS_GPIO_H__
 #define _IFXMIPS_GPIO_H__

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ioctl.h
deleted file mode 100644 (file)
index 58cdd7d..0000000
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ioctl.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
- */
-#ifndef _IFXMIPS_IOCTL_H__
-#define _IFXMIPS_IOCTL_H__
-
-/*------------ LED */
-
-struct ifxmips_port_ioctl_parm
-{
-       int port;
-       int pin;
-       int value;
-};
-
-#define IFXMIPS_PORT_IOC_MAGIC         0xbf
-#define IFXMIPS_PORT_IOCOD                     _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCPUDSEL         _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCPUDEN          _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCSTOFF          _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCDIR                    _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCOUTPUT         _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCINPUT          _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCALTSEL0                _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct ifxmips_port_ioctl_parm)
-#define IFXMIPS_PORT_IOCALTSEL1                _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct ifxmips_port_ioctl_parm)
-
-#endif

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h
index 6017df0acef99c6b6cf027f525b195ae05d8eda1..07db10b02c76c99c89c0e216e44064f3ef37f1f5 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h
@@ -15,7 +15,6 @@
  *
  *   Copyright (C) 2005 infineon
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
  */
 #ifndef _IFXMIPS_IRQ__
 #define _IFXMIPS_IRQ__

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
index c4a9929f6bc920dc0679c6bb9e4f2f2a9b620aba..5e0d7f3e1db3196eace6930c0cd31fbfcbcc9898 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
@@ -15,8 +15,12 @@
  *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
  */
+#ifndef _IFXMIPS_LED_H__ 
+#define _IFXMIPS_LED_H__
 
 extern void ifxmips_led_set(unsigned int led);
 extern void ifxmips_led_clear(unsigned int led);
 extern void ifxmips_led_blink_set(unsigned int led);
 extern void ifxmips_led_blink_clear(unsigned int led);
+
+#endif

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h
deleted file mode 100644 (file)
index 2f7e967..0000000
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef IFXMIPS_MII0_H
-#define IFXMIPS_MII0_H
-
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- */
-
-#include <linux/netdevice.h>
-
-struct ifxmips_mii_priv {
-    struct net_device_stats stats;
-    struct dma_device_info *dma_device;
-    struct sk_buff *skb;
-};
-
-struct ifxmips_mac {
-       unsigned char mac[6];
-};
-
-#endif

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_orig.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_orig.h
deleted file mode 100644 (file)
index 0c8aa98..0000000
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_orig.h
+++ /dev/null
@@ -1,2021 +0,0 @@
-#ifndef IFXMIPS_H
-#define IFXMIPS_H
-/******************************************************************************
-       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
-
-                               No Warranty
-   Because the program is licensed free of charge, there is no warranty for 
-   the program, to the extent permitted by applicable law.  Except when     
-   otherwise stated in writing the copyright holders and/or other parties   
-   provide the program "as is" without warranty of any kind, either         
-   expressed or implied, including, but not limited to, the implied         
-   warranties of merchantability and fitness for a particular purpose. The  
-   entire risk as to the quality and performance of the program is with     
-   you.  should the program prove defective, you assume the cost of all     
-   necessary servicing, repair or correction.                               
-                                                                            
-   In no event unless required by applicable law or agreed to in writing    
-   will any copyright holder, or any other party who may modify and/or      
-   redistribute the program as permitted above, be liable to you for        
-   damages, including any general, special, incidental or consequential     
-   damages arising out of the use or inability to use the program           
-   (including but not limited to loss of data or data being rendered        
-   inaccurate or losses sustained by you or third parties or a failure of   
-   the program to operate with any other programs), even if such holder or  
-   other party has been advised of the possibility of such damages. 
-******************************************************************************/
-
-/***********************************************************************/
-/*  Module      :  WDT register address and bits                       */
-/***********************************************************************/
-
-#define BOARD_SYSTEM_TYPE       "IFXMIPS"
-
-#define IFXMIPS_BIU_WDT                           (KSEG1+0x1F880000)
-
-/***Watchdog Timer Control Register ***/
-#define IFXMIPS_BIU_WDT_CR                   ((volatile u32*)(IFXMIPS_BIU_WDT + 0x03F0))
-#define IFXMIPS_BIU_WDT_CR_GEN               (1 << 31)
-#define IFXMIPS_BIU_WDT_CR_DSEN              (1 << 30)
-#define IFXMIPS_BIU_WDT_CR_LPEN              (1 << 29)
-#define IFXMIPS_BIU_WDT_CR_PWL_GET(value)    (((value) >> 26) & ((1 << 2) - 1))
-#define IFXMIPS_BIU_WDT_CR_PWL_SET(value)    (((( 1 << 2) - 1) & (value)) << 26)
-#define IFXMIPS_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
-#define IFXMIPS_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
-#define IFXMIPS_BIU_WDT_CR_PW_GET(value)     (((value) >> 16) & ((1 << 8) - 1))
-#define IFXMIPS_BIU_WDT_CR_PW_SET(value)     (((( 1 << 8) - 1) & (value)) << 16)
-#define IFXMIPS_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
-#define IFXMIPS_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Watchdog Timer Status Register***/
-#define IFXMIPS_BIU_WDT_SR                   ((volatile u32*)(IFXMIPS_BIU_WDT + 0x03F8))
-#define IFXMIPS_BIU_WDT_SR_EN                (1 << 31)
-#define IFXMIPS_BIU_WDT_SR_AE                (1 << 30)
-#define IFXMIPS_BIU_WDT_SR_PRW               (1 << 29)
-#define IFXMIPS_BIU_WDT_SR_EXP               (1 << 28)
-#define IFXMIPS_BIU_WDT_SR_PWD               (1 << 27)
-#define IFXMIPS_BIU_WDT_SR_DS                (1 << 26)
-#define IFXMIPS_BIU_WDT_SR_VALUE_GET(value)  (((value) >> 0) & ((1 << 16) - 1))
-#define IFXMIPS_BIU_WDT_SR_VALUE_SET(value)  (((( 1 << 16) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  PMU register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_PMU                            (KSEG1+0x1F102000)
-
-/* PMU Power down Control Register */
-#define IFXMIPS_PMU_PWDCR                        ((volatile u32*)(IFXMIPS_PMU+0x001C))
-#define IFXMIPS_PMU_PWDCR_GPT                                  (1 << 12)
-#define IFXMIPS_PMU_PWDCR_FPI                                  (1 << 14)
-
-
-/* PMU Status Register */
-#define IFXMIPS_PMU_SR                           ((volatile u32*)(IFXMIPS_PMU+0x0020))
-
-#define IFXMIPS_PMU_DMA_SHIFT                    5
-#define IFXMIPS_PMU_PPE_SHIFT                    13
-#define IFXMIPS_PMU_SDIO_SHIFT                   16
-#define IFXMIPS_PMU_ETOP_SHIFT                   22
-#define IFXMIPS_PMU_ENET0_SHIFT                  24
-#define IFXMIPS_PMU_ENET1_SHIFT                  25
-
-/***********************************************************************/
-/*  Module      :  RCU register address and bits                       */
-/***********************************************************************/
-#define IFXMIPS_RCU_BASE_ADDR          (0xBF203000)
-
-#define IFXMIPS_RCU_REQ                        (0x0010 + IFXMIPS_RCU_BASE_ADDR)        /* will remove this, pls use IFXMIPS_RCU_RST_REQ */
-
-#define IFXMIPS_RCU_RST_REQ              ((volatile u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
-#define IFXMIPS_RCU_RST_STAT             ((volatile u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0014))
-#define IFXMIPS_RST_ALL                  (0x40000000)
-
-/***Reset Request Register***/
-#define IFXMIPS_RCU_RST_REQ_CPU0                 (1 << 31)
-#define IFXMIPS_RCU_RST_REQ_CPU1                 (1 << 3)
-#define IFXMIPS_RCU_RST_REQ_CPUSUB               (1 << 29)
-#define IFXMIPS_RCU_RST_REQ_HRST                 (1 << 28)
-#define IFXMIPS_RCU_RST_REQ_WDT0                 (1 << 27)
-#define IFXMIPS_RCU_RST_REQ_WDT1                 (1 << 26)
-#define IFXMIPS_RCU_RST_REQ_CFG_GET(value)       (((value) >> 23) & ((1 << 3) - 1))
-#define IFXMIPS_RCU_RST_REQ_CFG_SET(value)       (((( 1 << 3) - 1) & (value)) << 23)
-#define IFXMIPS_RCU_RST_REQ_SWTBOOT              (1 << 22)
-#define IFXMIPS_RCU_RST_REQ_DMA                  (1 << 21)
-#define IFXMIPS_RCU_RST_REQ_ARC_JTAG              (1 << 20)
-#define IFXMIPS_RCU_RST_REQ_ETHPHY0              (1 << 19)
-#define IFXMIPS_RCU_RST_REQ_CPU0_BR              (1 << 18)
-
-#define DANBUE_RCU_RST_REQ_AFE                 (1 << 11)
-#define DANBUE_RCU_RST_REQ_DFE                 (1 << 7)
-
-/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
-#define IFXMIPS_RCU_RST_REQ_ALL                  IFXMIPS_RST_ALL
-
-#define IFXMIPS_RCU_STAT                       (0x0014 + IFXMIPS_RCU_BASE_ADDR)
-#define IFXMIPS_RCU_RST_SR             ( (volatile u32 *)(IFXMIPS_RCU_STAT))   /* will remove this, pls use IFXMIPS_RCU_RST_STAT */
-
-/*#define IFXMIPS_RCU_MON                  (0x0030 + IFXMIPS_RCU_BASE_ADDR) */
-
-/***********************************************************************/
-/*  Module      :  BCU  register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_BCU_BASE_ADDR                  (KSEG1+0x1E100000)
-
-/***BCU Control Register (0010H)***/
-#define IFXMIPS_BCU_CON                          ((volatile u32*)(0x0010 + IFXMIPS_BCU_BASE_ADDR))
-#define IFXMIPS_BCU_BCU_CON_SPC (value)                (((( 1 << 8) - 1) & (value)) << 24)
-#define IFXMIPS_BCU_BCU_CON_SPE                              (1 << 19)
-#define IFXMIPS_BCU_BCU_CON_PSE                              (1 << 18)
-#define IFXMIPS_BCU_BCU_CON_DBG                              (1 << 16)
-#define IFXMIPS_BCU_BCU_CON_TOUT (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***BCU Error Control Capture Register (0020H)***/
-#define IFXMIPS_BCU_ECON                         ((volatile u32*)(0x0020 + IFXMIPS_BCU_BASE_ADDR))
-#define IFXMIPS_BCU_BCU_ECON_TAG (value)                (((( 1 << 4) - 1) & (value)) << 24)
-#define IFXMIPS_BCU_BCU_ECON_RDN                              (1 << 23)
-#define IFXMIPS_BCU_BCU_ECON_WRN                              (1 << 22)
-#define IFXMIPS_BCU_BCU_ECON_SVM                              (1 << 21)
-#define IFXMIPS_BCU_BCU_ECON_ACK (value)                (((( 1 << 2) - 1) & (value)) << 19)
-#define IFXMIPS_BCU_BCU_ECON_ABT                              (1 << 18)
-#define IFXMIPS_BCU_BCU_ECON_RDY                              (1 << 17)
-#define IFXMIPS_BCU_BCU_ECON_TOUT                             (1 << 16)
-#define IFXMIPS_BCU_BCU_ECON_ERRCNT (value)             (((( 1 << 16) - 1) & (value)) << 0)
-#define IFXMIPS_BCU_BCU_ECON_OPC (value)                (((( 1 << 4) - 1) & (value)) << 28)
-
-/***BCU Error Address Capture Register (0024 H)***/
-#define IFXMIPS_BCU_EADD                       ((volatile u32*)(0x0024 + IFXMIPS_BCU_BASE_ADDR))
-
-/***BCU Error Data Capture Register (0028H)***/
-#define IFXMIPS_BCU_EDAT                       ((volatile u32*)(0x0028 + IFXMIPS_BCU_BASE_ADDR))
-#define IFXMIPS_BCU_IRNEN                      ((volatile u32*)(0x00F4 + IFXMIPS_BCU_BASE_ADDR))
-#define IFXMIPS_BCU_IRNICR                     ((volatile u32*)(0x00F8 + IFXMIPS_BCU_BASE_ADDR))
-#define IFXMIPS_BCU_IRNCR                      ((volatile u32*)(0x00FC + IFXMIPS_BCU_BASE_ADDR))
-
-/***********************************************************************/
-/*  Module      :  MBC register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_MBC                          (0xBF103000)
-/***********************************************************************/
-
-/***Mailbox CPU Configuration Register***/
-#define IFXMIPS_MBC_MBC_CFG                      ((volatile u32*)(IFXMIPS_MBC+ 0x0080))
-#define IFXMIPS_MBC_MBC_CFG_SWAP (value)               (((( 1 << 2) - 1) & (value)) << 6)
-#define IFXMIPS_MBC_MBC_CFG_RES                              (1 << 5)
-#define IFXMIPS_MBC_MBC_CFG_FWID (value)               (((( 1 << 4) - 1) & (value)) << 1)
-#define IFXMIPS_MBC_MBC_CFG_SIZE                            (1 << 0)
-
-/***Mailbox CPU Interrupt Status Register***/
-#define IFXMIPS_MBC_MBC_ISR                      ((volatile u32*)(IFXMIPS_MBC+ 0x0084))
-#define IFXMIPS_MBC_MBC_ISR_B3DA                            (1 << 31)
-#define IFXMIPS_MBC_MBC_ISR_B2DA                            (1 << 30)
-#define IFXMIPS_MBC_MBC_ISR_B1E                              (1 << 29)
-#define IFXMIPS_MBC_MBC_ISR_B0E                              (1 << 28)
-#define IFXMIPS_MBC_MBC_ISR_WDT                              (1 << 27)
-#define IFXMIPS_MBC_MBC_ISR_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask Register***/
-#define IFXMIPS_MBC_MBC_MSK                      ((volatile u32*)(IFXMIPS_MBC+ 0x0088))
-#define IFXMIPS_MBC_MBC_MSK_B3DA                            (1 << 31)
-#define IFXMIPS_MBC_MBC_MSK_B2DA                            (1 << 30)
-#define IFXMIPS_MBC_MBC_MSK_B1E                              (1 << 29)
-#define IFXMIPS_MBC_MBC_MSK_B0E                              (1 << 28)
-#define IFXMIPS_MBC_MBC_MSK_WDT                              (1 << 27)
-#define IFXMIPS_MBC_MBC_MSK_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 01 Register***/
-#define IFXMIPS_MBC_MBC_MSK01                    ((volatile u32*)(IFXMIPS_MBC+ 0x008C))
-#define IFXMIPS_MBC_MBC_MSK01_B3DA                            (1 << 31)
-#define IFXMIPS_MBC_MBC_MSK01_B2DA                            (1 << 30)
-#define IFXMIPS_MBC_MBC_MSK01_B1E                              (1 << 29)
-#define IFXMIPS_MBC_MBC_MSK01_B0E                              (1 << 28)
-#define IFXMIPS_MBC_MBC_MSK01_WDT                              (1 << 27)
-#define IFXMIPS_MBC_MBC_MSK01_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 10 Register***/
-#define IFXMIPS_MBC_MBC_MSK10                    ((volatile u32*)(IFXMIPS_MBC+ 0x0090))
-#define IFXMIPS_MBC_MBC_MSK10_B3DA                            (1 << 31)
-#define IFXMIPS_MBC_MBC_MSK10_B2DA                            (1 << 30)
-#define IFXMIPS_MBC_MBC_MSK10_B1E                              (1 << 29)
-#define IFXMIPS_MBC_MBC_MSK10_B0E                              (1 << 28)
-#define IFXMIPS_MBC_MBC_MSK10_WDT                              (1 << 27)
-#define IFXMIPS_MBC_MBC_MSK10_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Short Command Register***/
-#define IFXMIPS_MBC_MBC_CMD                      ((volatile u32*)(IFXMIPS_MBC+ 0x0094))
-#define IFXMIPS_MBC_MBC_CMD_CS270 (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***Mailbox CPU Input Data of Buffer 0***/
-#define IFXMIPS_MBC_MBC_ID0                      ((volatile u32*)(IFXMIPS_MBC+ 0x0000))
-#define IFXMIPS_MBC_MBC_ID0_INDATA
-
-/***Mailbox CPU Input Data of Buffer 1***/
-#define IFXMIPS_MBC_MBC_ID1                      ((volatile u32*)(IFXMIPS_MBC+ 0x0020))
-#define IFXMIPS_MBC_MBC_ID1_INDATA
-
-/***Mailbox CPU Output Data of Buffer 2***/
-#define IFXMIPS_MBC_MBC_OD2                      ((volatile u32*)(IFXMIPS_MBC+ 0x0040))
-#define IFXMIPS_MBC_MBC_OD2_OUTDATA
-
-/***Mailbox CPU Output Data of Buffer 3***/
-#define IFXMIPS_MBC_MBC_OD3                      ((volatile u32*)(IFXMIPS_MBC+ 0x0060))
-#define IFXMIPS_MBC_MBC_OD3_OUTDATA
-
-/***Mailbox CPU Control Register of Buffer 0***/
-#define IFXMIPS_MBC_MBC_CR0                      ((volatile u32*)(IFXMIPS_MBC+ 0x0004))
-#define IFXMIPS_MBC_MBC_CR0_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 1***/
-#define IFXMIPS_MBC_MBC_CR1                      ((volatile u32*)(IFXMIPS_MBC+ 0x0024))
-#define IFXMIPS_MBC_MBC_CR1_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 2***/
-#define IFXMIPS_MBC_MBC_CR2                      ((volatile u32*)(IFXMIPS_MBC+ 0x0044))
-#define IFXMIPS_MBC_MBC_CR2_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 3***/
-#define IFXMIPS_MBC_MBC_CR3                      ((volatile u32*)(IFXMIPS_MBC+ 0x0064))
-#define IFXMIPS_MBC_MBC_CR3_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Free Space of Buffer 0***/
-#define IFXMIPS_MBC_MBC_FS0                      ((volatile u32*)(IFXMIPS_MBC+ 0x0008))
-#define IFXMIPS_MBC_MBC_FS0_FS
-
-/***Mailbox CPU Free Space of Buffer 1***/
-#define IFXMIPS_MBC_MBC_FS1                      ((volatile u32*)(IFXMIPS_MBC+ 0x0028))
-#define IFXMIPS_MBC_MBC_FS1_FS
-
-/***Mailbox CPU Free Space of Buffer 2***/
-#define IFXMIPS_MBC_MBC_FS2                      ((volatile u32*)(IFXMIPS_MBC+ 0x0048))
-#define IFXMIPS_MBC_MBC_FS2_FS
-
-/***Mailbox CPU Free Space of Buffer 3***/
-#define IFXMIPS_MBC_MBC_FS3                      ((volatile u32*)(IFXMIPS_MBC+ 0x0068))
-#define IFXMIPS_MBC_MBC_FS3_FS
-
-/***Mailbox CPU Data Available in Buffer 0***/
-#define IFXMIPS_MBC_MBC_DA0                      ((volatile u32*)(IFXMIPS_MBC+ 0x000C))
-#define IFXMIPS_MBC_MBC_DA0_DA
-
-/***Mailbox CPU Data Available in Buffer 1***/
-#define IFXMIPS_MBC_MBC_DA1                      ((volatile u32*)(IFXMIPS_MBC+ 0x002C))
-#define IFXMIPS_MBC_MBC_DA1_DA
-
-/***Mailbox CPU Data Available in Buffer 2***/
-#define IFXMIPS_MBC_MBC_DA2                      ((volatile u32*)(IFXMIPS_MBC+ 0x004C))
-#define IFXMIPS_MBC_MBC_DA2_DA
-
-/***Mailbox CPU Data Available in Buffer 3***/
-#define IFXMIPS_MBC_MBC_DA3                      ((volatile u32*)(IFXMIPS_MBC+ 0x006C))
-#define IFXMIPS_MBC_MBC_DA3_DA
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
-#define IFXMIPS_MBC_MBC_IABS0                    ((volatile u32*)(IFXMIPS_MBC+ 0x0010))
-#define IFXMIPS_MBC_MBC_IABS0_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
-#define IFXMIPS_MBC_MBC_IABS1                    ((volatile u32*)(IFXMIPS_MBC+ 0x0030))
-#define IFXMIPS_MBC_MBC_IABS1_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
-#define IFXMIPS_MBC_MBC_IABS2                    ((volatile u32*)(IFXMIPS_MBC+ 0x0050))
-#define IFXMIPS_MBC_MBC_IABS2_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
-#define IFXMIPS_MBC_MBC_IABS3                    ((volatile u32*)(IFXMIPS_MBC+ 0x0070))
-#define IFXMIPS_MBC_MBC_IABS3_IABS
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
-#define IFXMIPS_MBC_MBC_ITMP0                    ((volatile u32*)(IFXMIPS_MBC+ 0x0014))
-#define IFXMIPS_MBC_MBC_ITMP0_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
-#define IFXMIPS_MBC_MBC_ITMP1                    ((volatile u32*)(IFXMIPS_MBC+ 0x0034))
-#define IFXMIPS_MBC_MBC_ITMP1_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
-#define IFXMIPS_MBC_MBC_ITMP2                    ((volatile u32*)(IFXMIPS_MBC+ 0x0054))
-#define IFXMIPS_MBC_MBC_ITMP2_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
-#define IFXMIPS_MBC_MBC_ITMP3                    ((volatile u32*)(IFXMIPS_MBC+ 0x0074))
-#define IFXMIPS_MBC_MBC_ITMP3_ITMP
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
-#define IFXMIPS_MBC_MBC_OABS0                    ((volatile u32*)(IFXMIPS_MBC+ 0x0018))
-#define IFXMIPS_MBC_MBC_OABS0_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
-#define IFXMIPS_MBC_MBC_OABS1                    ((volatile u32*)(IFXMIPS_MBC+ 0x0038))
-#define IFXMIPS_MBC_MBC_OABS1_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
-#define IFXMIPS_MBC_MBC_OABS2                    ((volatile u32*)(IFXMIPS_MBC+ 0x0058))
-#define IFXMIPS_MBC_MBC_OABS2_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
-#define IFXMIPS_MBC_MBC_OABS3                    ((volatile u32*)(IFXMIPS_MBC+ 0x0078))
-#define IFXMIPS_MBC_MBC_OABS3_OABS
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
-#define IFXMIPS_MBC_MBC_OTMP0                    ((volatile u32*)(IFXMIPS_MBC+ 0x001C))
-#define IFXMIPS_MBC_MBC_OTMP0_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
-#define IFXMIPS_MBC_MBC_OTMP1                    ((volatile u32*)(IFXMIPS_MBC+ 0x003C))
-#define IFXMIPS_MBC_MBC_OTMP1_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
-#define IFXMIPS_MBC_MBC_OTMP2                    ((volatile u32*)(IFXMIPS_MBC+ 0x005C))
-#define IFXMIPS_MBC_MBC_OTMP2_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
-#define IFXMIPS_MBC_MBC_OTMP3                    ((volatile u32*)(IFXMIPS_MBC+ 0x007C))
-#define IFXMIPS_MBC_MBC_OTMP3_OTMP
-
-/***DSP Control Register***/
-#define IFXMIPS_MBC_DCTRL                        ((volatile u32*)(IFXMIPS_MBC+ 0x00A0))
-#define IFXMIPS_MBC_DCTRL_BA                              (1 << 0)
-#define IFXMIPS_MBC_DCTRL_BMOD (value)               (((( 1 << 3) - 1) & (value)) << 1)
-#define IFXMIPS_MBC_DCTRL_IDL                              (1 << 4)
-#define IFXMIPS_MBC_DCTRL_RES                              (1 << 15)
-
-/***DSP Status Register***/
-#define IFXMIPS_MBC_DSTA                         ((volatile u32*)(IFXMIPS_MBC+ 0x00A4))
-#define IFXMIPS_MBC_DSTA_IDLE                            (1 << 0)
-#define IFXMIPS_MBC_DSTA_PD                              (1 << 1)
-
-/***DSP Test 1 Register***/
-#define IFXMIPS_MBC_DTST1                        ((volatile u32*)(IFXMIPS_MBC+ 0x00A8))
-#define IFXMIPS_MBC_DTST1_ABORT                          (1 << 0)
-#define IFXMIPS_MBC_DTST1_HWF32                          (1 << 1)
-#define IFXMIPS_MBC_DTST1_HWF4M                          (1 << 2)
-#define IFXMIPS_MBC_DTST1_HWFOP                          (1 << 3)
-
-/***********************************************************************/
-/*  Module      :  MEI register address and bits                       */
-/***********************************************************************/
-#define MEI_SPACE_ACCESS       0xBE116000
-
-/***   Register address offsets, relative to MEI_SPACE_ADDRESS ***/
-#define MEI_DATA_XFR                           ((volatile u32*)(0x0000 + MEI_SPACE_ACCESS))
-#define        MEI_VERSION                             ((volatile u32*)(0x0004 + MEI_SPACE_ACCESS))
-#define        MEI_ARC_GP_STAT                         ((volatile u32*)(0x0008 + MEI_SPACE_ACCESS))
-#define MEI_DATA_XFR_STAT                      ((volatile u32*)(0x000C + MEI_SPACE_ACCESS))
-#define        MEI_XFR_ADDR                            ((volatile u32*)(0x0010 + MEI_SPACE_ACCESS))
-#define MEI_MAX_WAIT                           ((volatile u32*)(0x0014 + MEI_SPACE_ACCESS))
-#define        MEI_TO_ARC_INT                          ((volatile u32*)(0x0018 + MEI_SPACE_ACCESS))
-#define        ARC_TO_MEI_INT                          ((volatile u32*)(0x001C + MEI_SPACE_ACCESS))
-#define        ARC_TO_MEI_INT_MASK                     ((volatile u32*)(0x0020 + MEI_SPACE_ACCESS))
-#define        MEI_DEBUG_WAD                           ((volatile u32*)(0x0024 + MEI_SPACE_ACCESS))
-#define MEI_DEBUG_RAD                          ((volatile u32*)(0x0028 + MEI_SPACE_ACCESS))
-#define        MEI_DEBUG_DATA                          ((volatile u32*)(0x002C + MEI_SPACE_ACCESS))
-#define        MEI_DEBUG_DEC                           ((volatile u32*)(0x0030 + MEI_SPACE_ACCESS))
-#define MEI_CONFIG                             ((volatile u32*)(0x0034 + MEI_SPACE_ACCESS))
-#define        MEI_RST_CONTROL                         ((volatile u32*)(0x0038 + MEI_SPACE_ACCESS))
-#define        MEI_DBG_MASTER                          ((volatile u32*)(0x003C + MEI_SPACE_ACCESS))
-#define        MEI_CLK_CONTROL                         ((volatile u32*)(0x0040 + MEI_SPACE_ACCESS))
-#define        MEI_BIST_CONTROL                        ((volatile u32*)(0x0044 + MEI_SPACE_ACCESS))
-#define        MEI_BIST_STAT                           ((volatile u32*)(0x0048 + MEI_SPACE_ACCESS))
-#define MEI_XDATA_BASE_SH                      ((volatile u32*)(0x004c + MEI_SPACE_ACCESS))
-#define MEI_XDATA_BASE                         ((volatile u32*)(0x0050 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR_BASE                      ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR0                          ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR1                          ((volatile u32*)(0x0058 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR2                          ((volatile u32*)(0x005C + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR3                          ((volatile u32*)(0x0060 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR4                          ((volatile u32*)(0x0064 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR5                          ((volatile u32*)(0x0068 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR6                          ((volatile u32*)(0x006C + MEI_SPACE_ACCESS)))
-#define MEI_XMEM_BAR7                          ((volatile u32*)(0x0070 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR8                          ((volatile u32*)(0x0074 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR9                          ((volatile u32*)(0x0078 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR10                         ((volatile u32*)(0x007C + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR11                         ((volatile u32*)(0x0080 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR12                         ((volatile u32*)(0x0084 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR13                         ((volatile u32*)(0x0088 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR14                         ((volatile u32*)(0x008C + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR15                         ((volatile u32*)(0x0090 + MEI_SPACE_ACCESS))
-#define MEI_XMEM_BAR16                         ((volatile u32*)(0x0094 + MEI_SPACE_ACCESS))
-
-/***********************************************************************/
-/*  Module      :  SSC1 register address and bits                      */
-/***********************************************************************/
-
-#define IFXMIPS_SSC1                           (KSEG1+0x1e100800)
-/***********************************************************************/
-/***SSC Clock Control Register***/
-#define IFXMIPS_SSC_CLC                        (0x0000)
-#define IFXMIPS_SSC_CLC_RMC(value)               (((( 1 << 8) - 1) & (value)) << 8)
-#define IFXMIPS_SSC_CLC_DISS                     (1 << 1)
-#define IFXMIPS_SSC_CLC_DISR                     (1 << 0)
-/***SSC Port Input Selection Register***/
-#define IFXMIPS_SSC_PISEL                        (0x0004)
-/***SSC Identification Register***/
-#define IFXMIPS_SSC_ID                           (0x0008)
-/***Control Register (Programming Mode)***/
-#define IFXMIPS_SSC_CON                                (0x0010)
-#define IFXMIPS_SSC_CON_RUEN                            (1 << 12)
-#define IFXMIPS_SSC_CON_TUEN                              (1 << 11)
-#define IFXMIPS_SSC_CON_AEN                              (1 << 10)
-#define IFXMIPS_SSC_CON_REN                              (1 << 9)
-#define IFXMIPS_SSC_CON_TEN                              (1 << 8)
-#define IFXMIPS_SSC_CON_LB                              (1 << 7)
-#define IFXMIPS_SSC_CON_PO                              (1 << 6)
-#define IFXMIPS_SSC_CON_PH                              (1 << 5)
-#define IFXMIPS_SSC_CON_HB                              (1 << 4)
-#define IFXMIPS_SSC_CON_BM(value)                      (((( 1 << 5) - 1) & (value)) << 16)
-#define IFXMIPS_SSC_CON_RX_OFF                          (1 << 1)
-#define IFXMIPS_SSC_CON_TX_OFF                          (1 << 0)
-/***SCC Status Register***/
-#define IFXMIPS_SSC_STATE                  (0x0014)
-#define IFXMIPS_SSC_STATE_EN                              (1 << 0)
-#define IFXMIPS_SSC_STATE_MS                              (1 << 1)
-#define IFXMIPS_SSC_STATE_BSY                              (1 << 13)
-#define IFXMIPS_SSC_STATE_RUE                              (1 << 12)
-#define IFXMIPS_SSC_STATE_TUE                              (1 << 11)
-#define IFXMIPS_SSC_STATE_AE                              (1 << 10)
-#define IFXMIPS_SSC_STATE_RE                              (1 << 9)
-#define IFXMIPS_SSC_STATE_TE                              (1 << 8)
-#define IFXMIPS_SSC_STATE_BC(value)                (((( 1 << 5) - 1) & (value)) << 16)
-/***SSC Write Hardware Modified Control Register***/
-#define IFXMIPS_SSC_WHBSTATE                   ( 0x0018)
-#define IFXMIPS_SSC_WHBSTATE_SETBE                          (1 << 15)
-#define IFXMIPS_SSC_WHBSTATE_SETPE                          (1 << 14)
-#define IFXMIPS_SSC_WHBSTATE_SETRE                          (1 << 13)
-#define IFXMIPS_SSC_WHBSTATE_SETTE                          (1 << 12)
-#define IFXMIPS_SSC_WHBSTATE_CLRBE                          (1 << 11)
-#define IFXMIPS_SSC_WHBSTATE_CLRPE                          (1 << 10)
-#define IFXMIPS_SSC_WHBSTATE_CLRRE                          (1 << 9)
-#define IFXMIPS_SSC_WHBSTATE_CLRTE                          (1 << 8)
-/***SSC Transmitter Buffer Register***/
-#define IFXMIPS_SSC_TB                       (0x0020)
-#define IFXMIPS_SSC_TB_TB_VALUE(value)          (((( 1 << 16) - 1) & (value)) << 0)
-/***SSC Receiver Buffer Register***/
-#define IFXMIPS_SSC_RB                       (0x0024)
-#define IFXMIPS_SSC_RB_RB_VALUE(value)          (((( 1 << 16) - 1) & (value)) << 0)
-/***SSC Receive FIFO Control Register***/
-#define IFXMIPS_SSC_RXFCON                   (0x0030)
-#define IFXMIPS_SSC_RXFCON_RXFITL(value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_SSC_RXFCON_RXTMEN                        (1 << 2)
-#define IFXMIPS_SSC_RXFCON_RXFLU                          (1 << 1)
-#define IFXMIPS_SSC_RXFCON_RXFEN                          (1 << 0)
-/***SSC Transmit FIFO Control Register***/
-#define IFXMIPS_SSC_TXFCON                   ( 0x0034)
-#define IFXMIPS_SSC_TXFCON_RXFITL(value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_SSC_TXFCON_TXTMEN                        (1 << 2)
-#define IFXMIPS_SSC_TXFCON_TXFLU                          (1 << 1)
-#define IFXMIPS_SSC_TXFCON_TXFEN                          (1 << 0)
-/***SSC FIFO Status Register***/
-#define IFXMIPS_SSC_FSTAT                    (0x0038)
-#define IFXMIPS_SSC_FSTAT_TXFFL(value)              (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_SSC_FSTAT_RXFFL(value)              (((( 1 << 6) - 1) & (value)) << 0)
-/***SSC Baudrate Timer Reload Register***/
-#define IFXMIPS_SSC_BR                       (0x0040)
-#define IFXMIPS_SSC_BR_BR_VALUE(value)          (((( 1 << 16) - 1) & (value)) << 0)
-#define IFXMIPS_SSC_BRSTAT                       (0x0044)
-#define IFXMIPS_SSC_SFCON                        (0x0060)
-#define IFXMIPS_SSC_SFSTAT                       (0x0064)
-#define IFXMIPS_SSC_GPOCON                       (0x0070)
-#define IFXMIPS_SSC_GPOSTAT                      (0x0074)
-#define IFXMIPS_SSC_WHBGPOSTAT                   (0x0078)
-#define IFXMIPS_SSC_RXREQ                        (0x0080)
-#define IFXMIPS_SSC_RXCNT                        (0x0084)
-/*DMA Registers in Bus Clock Domain*/
-#define IFXMIPS_SSC_DMA_CON                      (0x00EC)
-/*interrupt Node Registers in Bus Clock Domain*/
-#define IFXMIPS_SSC_IRNEN                        (0x00F4)
-#define IFXMIPS_SSC_IRNCR                        (0x00F8)
-#define IFXMIPS_SSC_IRNICR                       (0x00FC)
-#define IFXMIPS_SSC_IRN_FIR                    0x8
-#define IFXMIPS_SSC_IRN_EIR                    0x4
-#define IFXMIPS_SSC_IRN_RIR                    0x2
-#define IFXMIPS_SSC_IRN_TIR                    0x1
-
-#define        IFXMIPS_SSC1_CLC                        ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_CLC))
-#define        IFXMIPS_SSC1_ID                 ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_ID))
-#define        IFXMIPS_SSC1_CON                        ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_CON))
-#define        IFXMIPS_SSC1_STATE                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_STATE))
-#define        IFXMIPS_SSC1_WHBSTATE                   ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_WHBSTATE))
-#define        IFXMIPS_SSC1_TB                 ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_TB))
-#define        IFXMIPS_SSC1_RB                 ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RB))
-#define        IFXMIPS_SSC1_FSTAT                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_FSTAT))
-#define        IFXMIPS_SSC1_PISEL                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_PISEL))
-#define        IFXMIPS_SSC1_RXFCON                     ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RXFCON))
-#define        IFXMIPS_SSC1_TXFCON                     ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_TXFCON))
-#define        IFXMIPS_SSC1_BR                 ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_BR))
-#define        IFXMIPS_SSC1_BRSTAT                     ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_BRSTAT))
-#define        IFXMIPS_SSC1_SFCON                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_SFCON))
-#define        IFXMIPS_SSC1_SFSTAT                     ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_SFSTAT))
-#define        IFXMIPS_SSC1_GPOCON                     ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_GPOCON))
-#define        IFXMIPS_SSC1_GPOSTAT                    ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_GPOSTAT))
-#define        IFXMIPS_SSC1_WHBGPOSTAT                 ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_WHBGPOSTAT))
-#define        IFXMIPS_SSC1_RXREQ                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RXREQ))
-#define        IFXMIPS_SSC1_RXCNT                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RXCNT))
-#define        IFXMIPS_SSC1_DMA_CON                    ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_DMA_CON))
-#define        IFXMIPS_SSC1_IRNEN                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_IRNEN))
-#define        IFXMIPS_SSC1_IRNICR                     ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_IRNICR))
-#define        IFXMIPS_SSC1_IRNCR                      ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_IRNCR))
-
-/***********************************************************************/
-/*  Module      :  GPIO register address and bits                       */
-/***********************************************************************/
-#define IFXMIPS_GPIO                     (0xBE100B00)
-/***Port 0 Data Output Register (0010H)***/
-#define IFXMIPS_GPIO_P0_OUT              ((volatile u32 *)(IFXMIPS_GPIO+ 0x0010))
-/***Port 1 Data Output Register (0040H)***/
-#define IFXMIPS_GPIO_P1_OUT              ((volatile u32 *)(IFXMIPS_GPIO+ 0x0040))
-/***Port 0 Data Input Register (0014H)***/
-#define IFXMIPS_GPIO_P0_IN               ((volatile u32 *)(IFXMIPS_GPIO+ 0x0014))
-/***Port 1 Data Input Register (0044H)***/
-#define IFXMIPS_GPIO_P1_IN               ((volatile u32 *)(IFXMIPS_GPIO+ 0x0044))
-/***Port 0 Direction Register (0018H)***/
-#define IFXMIPS_GPIO_P0_DIR              ((volatile u32 *)(IFXMIPS_GPIO+ 0x0018))
-/***Port 1 Direction Register (0048H)***/
-#define IFXMIPS_GPIO_P1_DIR              ((volatile u32 *)(IFXMIPS_GPIO+ 0x0048))
-/***Port 0 Alternate Function Select Register 0 (001C H) ***/
-#define IFXMIPS_GPIO_P0_ALTSEL0          ((volatile u32 *)(IFXMIPS_GPIO+ 0x001C))
-/***Port 1 Alternate Function Select Register 0 (004C H) ***/
-#define IFXMIPS_GPIO_P1_ALTSEL0          ((volatile u32 *)(IFXMIPS_GPIO+ 0x004C))
-/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
-#define IFXMIPS_GPIO_P0_ALTSEL1          ((volatile u32 *)(IFXMIPS_GPIO+ 0x0020))
-/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
-#define IFXMIPS_GPIO_P1_ALTSEL1          ((volatile u32 *)(IFXMIPS_GPIO+ 0x0050))
-/***Port 0 Open Drain Control Register (0024H)***/
-#define IFXMIPS_GPIO_P0_OD               ((volatile u32 *)(IFXMIPS_GPIO+ 0x0024))
-/***Port 1 Open Drain Control Register (0054H)***/
-#define IFXMIPS_GPIO_P1_OD               ((volatile u32 *)(IFXMIPS_GPIO+ 0x0054))
-/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
-#define IFXMIPS_GPIO_P0_STOFF            ((volatile u32 *)(IFXMIPS_GPIO+ 0x0028))
-/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
-#define IFXMIPS_GPIO_P1_STOFF            ((volatile u32 *)(IFXMIPS_GPIO+ 0x0058))
-/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
-#define IFXMIPS_GPIO_P0_PUDSEL           ((volatile u32 *)(IFXMIPS_GPIO+ 0x002C))
-/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
-#define IFXMIPS_GPIO_P1_PUDSEL           ((volatile u32 *)(IFXMIPS_GPIO+ 0x005C))
-/***Port 0 Pull Up Device Enable Register (0030 H)***/
-#define IFXMIPS_GPIO_P0_PUDEN            ((volatile u32 *)(IFXMIPS_GPIO+ 0x0030))
-/***Port 1 Pull Up Device Enable Register (0060 H)***/
-#define IFXMIPS_GPIO_P1_PUDEN            ((volatile u32 *)(IFXMIPS_GPIO+ 0x0060))
-/***********************************************************************/
-/*  Module      :  CGU register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_CGU                          (0xBF103000)
-/***********************************************************************/
-/***CGU Clock PLL0 ***/
-#define IFXMIPS_CGU_PLL0_CFG                   ((volatile u32*)(IFXMIPS_CGU+ 0x0004))
-/***CGU Clock PLL1 ***/
-#define IFXMIPS_CGU_PLL1_CFG                   ((volatile u32*)(IFXMIPS_CGU+ 0x0008))
-/***CGU Clock SYS Mux Register***/
-#define IFXMIPS_CGU_SYS                        ((volatile u32*)(IFXMIPS_CGU+ 0x0010))
-/***CGU Interface Clock Control Register***/
-#define IFXMIPS_CGU_IFCCR                        ((volatile u32*)(IFXMIPS_CGU+ 0x0018))
-/***CGU PCI Clock Control Register**/
-#define IFXMIPS_CGU_PCICR                          ((volatile u32*)(IFXMIPS_CGU+ 0x0034))
-#define CLOCK_60M                60000000
-#define CLOCK_83M                83333333
-#define CLOCK_111M               111111111
-#define CLOCK_133M               133333333
-#define CLOCK_167M               166666667
-#define CLOCK_333M               333333333
-
-/***********************************************************************/
-/*  Module      :  MCD register address and bits                       */
-/***********************************************************************/
-#define IFXMIPS_MCD                                    (KSEG1+0x1F106000)
-
-/***Manufacturer Identification Register***/
-#define IFXMIPS_MCD_MANID                              ((volatile u32*)(IFXMIPS_MCD+ 0x0024))
-#define IFXMIPS_MCD_MANID_MANUF(value)                 (((( 1 << 11) - 1) & (value)) << 5)
-
-/***Chip Identification Register***/
-#define IFXMIPS_MCD_CHIPID                             ((volatile u32*)(IFXMIPS_MCD+ 0x0028))
-#define IFXMIPS_MCD_CHIPID_VERSION_GET(value)             (((value) >> 28) & ((1 << 4) - 1))
-#define IFXMIPS_MCD_CHIPID_VERSION_SET(value)             (((( 1 << 4) - 1) & (value)) << 28)
-#define IFXMIPS_MCD_CHIPID_PART_NUMBER_GET(value)         (((value) >> 12) & ((1 << 16) - 1))
-#define IFXMIPS_MCD_CHIPID_PART_NUMBER_SET(value)         (((( 1 << 16) - 1) & (value)) << 12)
-#define IFXMIPS_MCD_CHIPID_MANID_GET(value)               (((value) >> 1) & ((1 << 11) - 1))
-#define IFXMIPS_MCD_CHIPID_MANID_SET(value)               (((( 1 << 11) - 1) & (value)) << 1)
-
-#define IFXMIPS_CHIPID_STANDARD                                0x00EB
-#define IFXMIPS_CHIPID_YANGTSE                         0x00ED
-
-/***Redesign Tracing Identification Register***/
-#define IFXMIPS_MCD_RTID                               ((volatile u32*)(IFXMIPS_MCD+ 0x002C))
-#define IFXMIPS_MCD_RTID_LC                              (1 << 15)
-#define IFXMIPS_MCD_RTID_RIX(value)                    (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  EBU register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_EBU                          (0xBE105300)
-
-/***********************************************************************/
-
-/***EBU Clock Control Register***/
-#define IFXMIPS_EBU_CLC                      ((volatile u32*)(IFXMIPS_EBU+ 0x0000))
-#define IFXMIPS_EBU_CLC_DISS                            (1 << 1)
-#define IFXMIPS_EBU_CLC_DISR                            (1 << 0)
-
-/***EBU Global Control Register***/
-#define IFXMIPS_EBU_CON                      ((volatile u32*)(IFXMIPS_EBU+ 0x0010))
-#define IFXMIPS_EBU_CON_DTACS (value)              (((( 1 << 3) - 1) & (value)) << 20)
-#define IFXMIPS_EBU_CON_DTARW (value)              (((( 1 << 3) - 1) & (value)) << 16)
-#define IFXMIPS_EBU_CON_TOUTC (value)              (((( 1 << 8) - 1) & (value)) << 8)
-#define IFXMIPS_EBU_CON_ARBMODE (value)            (((( 1 << 2) - 1) & (value)) << 6)
-#define IFXMIPS_EBU_CON_ARBSYNC                      (1 << 5)
-#define IFXMIPS_EBU_CON_1                              (1 << 3)
-
-/***EBU Address Select Register 0***/
-#define IFXMIPS_EBU_ADDSEL0                  ((volatile u32*)(IFXMIPS_EBU+ 0x0020))
-#define IFXMIPS_EBU_ADDSEL0_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define IFXMIPS_EBU_ADDSEL0_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_ADDSEL0_MIRRORE                      (1 << 1)
-#define IFXMIPS_EBU_ADDSEL0_REGEN                          (1 << 0)
-
-/***EBU Address Select Register 1***/
-#define IFXMIPS_EBU_ADDSEL1                  ((volatile u32*)(IFXMIPS_EBU+ 0x0024))
-#define IFXMIPS_EBU_ADDSEL1_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define IFXMIPS_EBU_ADDSEL1_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_ADDSEL1_MIRRORE                      (1 << 1)
-#define IFXMIPS_EBU_ADDSEL1_REGEN                          (1 << 0)
-
-/***EBU Address Select Register 2***/
-#define IFXMIPS_EBU_ADDSEL2                  ((volatile u32*)(IFXMIPS_EBU+ 0x0028))
-#define IFXMIPS_EBU_ADDSEL2_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define IFXMIPS_EBU_ADDSEL2_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_ADDSEL2_MIRRORE                      (1 << 1)
-#define IFXMIPS_EBU_ADDSEL2_REGEN                          (1 << 0)
-
-/***EBU Address Select Register 3***/
-#define IFXMIPS_EBU_ADDSEL3                  ((volatile u32*)(IFXMIPS_EBU+ 0x0028))
-#define IFXMIPS_EBU_ADDSEL3_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define IFXMIPS_EBU_ADDSEL3_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_ADDSEL3_MIRRORE                      (1 << 1)
-#define IFXMIPS_EBU_ADDSEL3_REGEN                          (1 << 0)
-
-/***EBU Bus Configuration Register 0***/
-#define IFXMIPS_EBU_BUSCON0                  ((volatile u32*)(IFXMIPS_EBU+ 0x0060))
-#define IFXMIPS_EBU_BUSCON0_WRDIS                          (1 << 31)
-#define IFXMIPS_EBU_BUSCON0_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
-#define IFXMIPS_EBU_BUSCON0_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
-#define IFXMIPS_EBU_BUSCON0_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
-#define IFXMIPS_EBU_BUSCON0_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
-#define IFXMIPS_EBU_BUSCON0_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
-#define IFXMIPS_EBU_BUSCON0_WAITINV                      (1 << 19)
-#define IFXMIPS_EBU_BUSCON0_SETUP                          (1 << 18)
-#define IFXMIPS_EBU_BUSCON0_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
-#define IFXMIPS_EBU_BUSCON0_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
-#define IFXMIPS_EBU_BUSCON0_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
-#define IFXMIPS_EBU_BUSCON0_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_BUSCON0_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define IFXMIPS_EBU_BUSCON0_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 1***/
-#define IFXMIPS_EBU_BUSCON1                  ((volatile u32*)(IFXMIPS_EBU+ 0x0064))
-#define IFXMIPS_EBU_BUSCON1_WRDIS                          (1 << 31)
-#define IFXMIPS_EBU_BUSCON1_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
-#define IFXMIPS_EBU_BUSCON1_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
-#define IFXMIPS_EBU_BUSCON1_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
-#define IFXMIPS_EBU_BUSCON1_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
-#define IFXMIPS_EBU_BUSCON1_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
-#define IFXMIPS_EBU_BUSCON1_WAITINV                      (1 << 19)
-#define IFXMIPS_EBU_BUSCON1_SETUP                          (1 << 18)
-#define IFXMIPS_EBU_BUSCON1_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
-#define IFXMIPS_EBU_BUSCON1_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
-#define IFXMIPS_EBU_BUSCON1_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
-#define IFXMIPS_EBU_BUSCON1_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_BUSCON1_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define IFXMIPS_EBU_BUSCON1_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 2***/
-#define IFXMIPS_EBU_BUSCON2                  ((volatile u32*)(IFXMIPS_EBU+ 0x0068))
-#define IFXMIPS_EBU_BUSCON2_WRDIS                          (1 << 31)
-#define IFXMIPS_EBU_BUSCON2_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
-#define IFXMIPS_EBU_BUSCON2_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
-#define IFXMIPS_EBU_BUSCON2_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
-#define IFXMIPS_EBU_BUSCON2_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
-#define IFXMIPS_EBU_BUSCON2_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
-#define IFXMIPS_EBU_BUSCON2_WAITINV                      (1 << 19)
-#define IFXMIPS_EBU_BUSCON2_SETUP                          (1 << 18)
-#define IFXMIPS_EBU_BUSCON2_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
-#define IFXMIPS_EBU_BUSCON2_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
-#define IFXMIPS_EBU_BUSCON2_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
-#define IFXMIPS_EBU_BUSCON2_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define IFXMIPS_EBU_BUSCON2_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define IFXMIPS_EBU_BUSCON2_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-#define IFXMIPS_EBU_PCC_CON                  ((volatile u32*)(IFXMIPS_EBU+ 0x0090))
-#define IFXMIPS_EBU_PCC_STAT                  ((volatile u32*)(IFXMIPS_EBU+ 0x0094))
-#define IFXMIPS_EBU_PCC_ISTAT                  ((volatile u32*)(IFXMIPS_EBU+ 0x00A0))
-#define IFXMIPS_EBU_PCC_IEN                  ((volatile u32*)(IFXMIPS_EBU+ 0x00A4))
-/***********************************************************************/
-/*  Module      :  SDRAM register address and bits                     */
-/***********************************************************************/
-
-#define IFXMIPS_SDRAM                        (0xBF800000)
-/***********************************************************************/
-
-/***MC Access Error Cause Register***/
-#define IFXMIPS_SDRAM_MC_ERRCAUSE                  ((volatile u32*)(IFXMIPS_SDRAM+ 0x0100))
-#define IFXMIPS_SDRAM_MC_ERRCAUSE_ERR                              (1 << 31)
-#define IFXMIPS_SDRAM_MC_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define IFXMIPS_SDRAM_MC_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
-#define IFXMIPS_SDRAM_MC_ERRCAUSE_Res (value)                (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***MC Access Error Address Register***/
-#define IFXMIPS_SDRAM_MC_ERRADDR                   ((volatile u32*)(IFXMIPS_SDRAM+ 0x0108))
-#define IFXMIPS_SDRAM_MC_ERRADDR_ADDR
-
-/***MC I/O General Purpose Register***/
-#define IFXMIPS_SDRAM_MC_IOGP                      ((volatile u32*)(IFXMIPS_SDRAM+ 0x0800))
-#define IFXMIPS_SDRAM_MC_IOGP_GPR6 (value)               (((( 1 << 4) - 1) & (value)) << 28)
-#define IFXMIPS_SDRAM_MC_IOGP_GPR5 (value)               (((( 1 << 4) - 1) & (value)) << 24)
-#define IFXMIPS_SDRAM_MC_IOGP_GPR4 (value)               (((( 1 << 4) - 1) & (value)) << 20)
-#define IFXMIPS_SDRAM_MC_IOGP_GPR3 (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define IFXMIPS_SDRAM_MC_IOGP_GPR2 (value)               (((( 1 << 4) - 1) & (value)) << 12)
-#define IFXMIPS_SDRAM_MC_IOGP_CPS                              (1 << 11)
-#define IFXMIPS_SDRAM_MC_IOGP_CLKDELAY (value)          (((( 1 << 3) - 1) & (value)) << 8)
-#define IFXMIPS_SDRAM_MC_IOGP_CLKRAT (value)             (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_SDRAM_MC_IOGP_RDDEL (value)              (((( 1 << 4) - 1) & (value)) << 0)
-
-/***MC Self Refresh Register***/
-#define IFXMIPS_SDRAM_MC_SELFRFSH                  ((volatile u32*)(IFXMIPS_SDRAM+ 0x0A00))
-#define IFXMIPS_SDRAM_MC_SELFRFSH_PWDS                            (1 << 1)
-#define IFXMIPS_SDRAM_MC_SELFRFSH_PWD                              (1 << 0)
-#define IFXMIPS_SDRAM_MC_SELFRFSH_Res (value)                (((( 1 << 30) - 1) & (value)) << 2)
-
-/***MC Enable Register***/
-#define IFXMIPS_SDRAM_MC_CTRLENA                   ((volatile u32*)(IFXMIPS_SDRAM+ 0x1000))
-#define IFXMIPS_SDRAM_MC_CTRLENA_ENA                              (1 << 0)
-#define IFXMIPS_SDRAM_MC_CTRLENA_Res (value)                (((( 1 << 31) - 1) & (value)) << 1)
-
-/***MC Mode Register Setup Code***/
-#define IFXMIPS_SDRAM_MC_MRSCODE                   ((volatile u32*)(IFXMIPS_SDRAM+ 0x1008))
-#define IFXMIPS_SDRAM_MC_MRSCODE_UMC (value)                (((( 1 << 5) - 1) & (value)) << 7)
-#define IFXMIPS_SDRAM_MC_MRSCODE_CL (value)                (((( 1 << 3) - 1) & (value)) << 4)
-#define IFXMIPS_SDRAM_MC_MRSCODE_WT                              (1 << 3)
-#define IFXMIPS_SDRAM_MC_MRSCODE_BL (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***MC Configuration Data-word Width Register***/
-#define IFXMIPS_SDRAM_MC_CFGDW                    ((volatile u32*)(IFXMIPS_SDRAM+ 0x1010))
-#define IFXMIPS_SDRAM_MC_CFGDW_DW (value)                (((( 1 << 4) - 1) & (value)) << 0)
-#define IFXMIPS_SDRAM_MC_CFGDW_Res (value)                (((( 1 << 28) - 1) & (value)) << 4)
-
-/***MC Configuration Physical Bank 0 Register***/
-#define IFXMIPS_SDRAM_MC_CFGPB0                    ((volatile u32*)(IFXMIPS_SDRAM+ 0x1018))
-#define IFXMIPS_SDRAM_MC_CFGPB0_MCSEN0 (value)             (((( 1 << 4) - 1) & (value)) << 12)
-#define IFXMIPS_SDRAM_MC_CFGPB0_BANKN0 (value)             (((( 1 << 4) - 1) & (value)) << 8)
-#define IFXMIPS_SDRAM_MC_CFGPB0_ROWW0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_SDRAM_MC_CFGPB0_COLW0 (value)              (((( 1 << 4) - 1) & (value)) << 0)
-#define IFXMIPS_SDRAM_MC_CFGPB0_Res (value)                (((( 1 << 16) - 1) & (value)) << 16)
-
-/***MC Latency Register***/
-#define IFXMIPS_SDRAM_MC_LATENCY                   ((volatile u32*)(IFXMIPS_SDRAM+ 0x1038))
-#define IFXMIPS_SDRAM_MC_LATENCY_TRP (value)                (((( 1 << 4) - 1) & (value)) << 16)
-#define IFXMIPS_SDRAM_MC_LATENCY_TRAS (value)               (((( 1 << 4) - 1) & (value)) << 12)
-#define IFXMIPS_SDRAM_MC_LATENCY_TRCD (value)               (((( 1 << 4) - 1) & (value)) << 8)
-#define IFXMIPS_SDRAM_MC_LATENCY_TDPL (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_SDRAM_MC_LATENCY_TDAL (value)               (((( 1 << 4) - 1) & (value)) << 0)
-#define IFXMIPS_SDRAM_MC_LATENCY_Res (value)                (((( 1 << 12) - 1) & (value)) << 20)
-
-/***MC Refresh Cycle Time Register***/
-#define IFXMIPS_SDRAM_MC_TREFRESH                  ((volatile u32*)(IFXMIPS_SDRAM+ 0x1040))
-#define IFXMIPS_SDRAM_MC_TREFRESH_TREF (value)               (((( 1 << 13) - 1) & (value)) << 0)
-#define IFXMIPS_SDRAM_MC_TREFRESH_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
-
-/***********************************************************************/
-/*  Module      :  GPTC register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_GPTC                   (KSEG1 + 0x1E100A00)
-#define IFXMIPS_GPTC_CLC               ((volatile u32*) (IFXMIPS_GPTC + 0x0000))
-#define IFXMIPS_GPTC_ID                ((volatile u32*) (IFXMIPS_GPTC + 0x0008))
-#define IFXMIPS_GPTC_IRNEN             ((volatile u32*) (IFXMIPS_GPTC + 0x00F4))
-#define IFXMIPS_GPTC_IRNICR    ((volatile u32*) (IFXMIPS_GPTC + 0x00F8)
-#define IFXMIPS_GPTC_IRNCR             ((volatile u32*) (IFXMIPS_GPTC + 0x00FC))
-
-#define IFXMIPS_GPTC_CON_1A    ((volatile u32*) (IFXMIPS_GPTC + 0x0010))
-#define IFXMIPS_GPTC_RUN_1A    ((volatile u32*) (IFXMIPS_GPTC + 0x0018))
-#define IFXMIPS_GPTC_RELOAD_1A ((volatile u32*) (IFXMIPS_GPTC + 0x0020))
-#define IFXMIPS_GPTC_COUNT_1A  ((volatile u32*) (IFXMIPS_GPTC + 0x0028))
-
-#define IFXMIPS_GPTC_CON_1B    ((volatile u32*) (IFXMIPS_GPTC + 0x0014))
-#define IFXMIPS_GPTC_RUN_1B    ((volatile u32*) (IFXMIPS_GPTC + 0x001C))
-#define IFXMIPS_GPTC_RELOAD_1B ((volatile u32*) (IFXMIPS_GPTC + 0x0024))
-#define IFXMIPS_GPTC_COUNT_1B  ((volatile u32*) (IFXMIPS_GPTC + 0x002C))
-
-#define IFXMIPS_GPTC_CON_2A    ((volatile u32*) (IFXMIPS_GPTC + 0x0030))
-#define IFXMIPS_GPTC_RUN_2A    ((volatile u32*) (IFXMIPS_GPTC + 0x0038))
-#define IFXMIPS_GPTC_RELOAD_2A ((volatile u32*) (IFXMIPS_GPTC + 0x0040))
-#define IFXMIPS_GPTC_COUNT_2A  ((volatile u32*) (IFXMIPS_GPTC + 0x0048))
-
-#define IFXMIPS_GPTC_CON_2B    ((volatile u32*) (IFXMIPS_GPTC + 0x0034))
-#define IFXMIPS_GPTC_RUN_2B    ((volatile u32*) (IFXMIPS_GPTC + 0x003C))
-#define IFXMIPS_GPTC_RELOAD_2B ((volatile u32*) (IFXMIPS_GPTC + 0x0044))
-#define IFXMIPS_GPTC_COUNT_2B  ((volatile u32*) (IFXMIPS_GPTC + 0x004C))
-
-/***********************************************************************/
-/*  Module      :  GPTU register address and bits                      */
-/***********************************************************************/
-
-#define IFXMIPS_GPTU                         (0xB8000300)
-/***********************************************************************/
-
-/***GPT Clock Control Register***/
-#define IFXMIPS_GPTU_GPT_CLC                      ((volatile u32*)(IFXMIPS_GPTU+ 0x0000))
-#define IFXMIPS_GPTU_GPT_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define IFXMIPS_GPTU_GPT_CLC_DISS                            (1 << 1)
-#define IFXMIPS_GPTU_GPT_CLC_DISR                            (1 << 0)
-
-/***GPT Timer 3 Control Register***/
-#define IFXMIPS_GPTU_GPT_T3CON                    ((volatile u32*)(IFXMIPS_GPTU+ 0x0014))
-#define IFXMIPS_GPTU_GPT_T3CON_T3RDIR                        (1 << 15)
-#define IFXMIPS_GPTU_GPT_T3CON_T3CHDIR                      (1 << 14)
-#define IFXMIPS_GPTU_GPT_T3CON_T3EDGE                        (1 << 13)
-#define IFXMIPS_GPTU_GPT_T3CON_BPS1 (value)               (((( 1 << 2) - 1) & (value)) << 11)
-#define IFXMIPS_GPTU_GPT_T3CON_T3OTL                          (1 << 10)
-#define IFXMIPS_GPTU_GPT_T3CON_T3UD                            (1 << 7)
-#define IFXMIPS_GPTU_GPT_T3CON_T3R                              (1 << 6)
-#define IFXMIPS_GPTU_GPT_T3CON_T3M (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define IFXMIPS_GPTU_GPT_T3CON_T3I (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write Hardware Modified Timer 3 Control Register
-If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define IFXMIPS_GPTU_GPT_WHBT3CON                 ((volatile u32*)(IFXMIPS_GPTU+ 0x004C))
-#define IFXMIPS_GPTU_GPT_WHBT3CON_SETT3CHDIR                (1 << 15)
-#define IFXMIPS_GPTU_GPT_WHBT3CON_CLRT3CHDIR                (1 << 14)
-#define IFXMIPS_GPTU_GPT_WHBT3CON_SETT3EDGE                  (1 << 13)
-#define IFXMIPS_GPTU_GPT_WHBT3CON_CLRT3EDGE                  (1 << 12)
-#define IFXMIPS_GPTU_GPT_WHBT3CON_SETT3OTL                  (1 << 11)
-#define IFXMIPS_GPTU_GPT_WHBT3CON_CLRT3OTL                  (1 << 10)
-
-/***GPT Timer 2 Control Register***/
-#define IFXMIPS_GPTU_GPT_T2CON                    ((volatile u32*)(IFXMIPS_GPTU+ 0x0010))
-#define IFXMIPS_GPTU_GPT_T2CON_TxRDIR                        (1 << 15)
-#define IFXMIPS_GPTU_GPT_T2CON_TxCHDIR                      (1 << 14)
-#define IFXMIPS_GPTU_GPT_T2CON_TxEDGE                        (1 << 13)
-#define IFXMIPS_GPTU_GPT_T2CON_TxIRDIS                      (1 << 12)
-#define IFXMIPS_GPTU_GPT_T2CON_TxRC                            (1 << 9)
-#define IFXMIPS_GPTU_GPT_T2CON_TxUD                            (1 << 7)
-#define IFXMIPS_GPTU_GPT_T2CON_TxR                              (1 << 6)
-#define IFXMIPS_GPTU_GPT_T2CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define IFXMIPS_GPTU_GPT_T2CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Control Register***/
-#define IFXMIPS_GPTU_GPT_T4CON                    ((volatile u32*)(IFXMIPS_GPTU+ 0x0018))
-#define IFXMIPS_GPTU_GPT_T4CON_TxRDIR                        (1 << 15)
-#define IFXMIPS_GPTU_GPT_T4CON_TxCHDIR                      (1 << 14)
-#define IFXMIPS_GPTU_GPT_T4CON_TxEDGE                        (1 << 13)
-#define IFXMIPS_GPTU_GPT_T4CON_TxIRDIS                      (1 << 12)
-#define IFXMIPS_GPTU_GPT_T4CON_TxRC                            (1 << 9)
-#define IFXMIPS_GPTU_GPT_T4CON_TxUD                            (1 << 7)
-#define IFXMIPS_GPTU_GPT_T4CON_TxR                              (1 << 6)
-#define IFXMIPS_GPTU_GPT_T4CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define IFXMIPS_GPTU_GPT_T4CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 2 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define IFXMIPS_GPTU_GPT_WHBT2CON                 ((volatile u32*)(IFXMIPS_GPTU+ 0x0048))
-#define IFXMIPS_GPTU_GPT_WHBT2CON_SETTxCHDIR                (1 << 15)
-#define IFXMIPS_GPTU_GPT_WHBT2CON_CLRTxCHDIR                (1 << 14)
-#define IFXMIPS_GPTU_GPT_WHBT2CON_SETTxEDGE                  (1 << 13)
-#define IFXMIPS_GPTU_GPT_WHBT2CON_CLRTxEDGE                  (1 << 12)
-
-/***GPT Write HW Modified Timer 4 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define IFXMIPS_GPTU_GPT_WHBT4CON                 ((volatile u32*)(IFXMIPS_GPTU+ 0x0050))
-#define IFXMIPS_GPTU_GPT_WHBT4CON_SETTxCHDIR                (1 << 15)
-#define IFXMIPS_GPTU_GPT_WHBT4CON_CLRTxCHDIR                (1 << 14)
-#define IFXMIPS_GPTU_GPT_WHBT4CON_SETTxEDGE                  (1 << 13)
-#define IFXMIPS_GPTU_GPT_WHBT4CON_CLRTxEDGE                  (1 << 12)
-
-/***GPT Capture Reload Register***/
-#define IFXMIPS_GPTU_GPT_CAPREL                   ((volatile u32*)(IFXMIPS_GPTU+ 0x0030))
-#define IFXMIPS_GPTU_GPT_CAPREL_CAPREL (value)             (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 2 Register***/
-#define IFXMIPS_GPTU_GPT_T2                       ((volatile u32*)(IFXMIPS_GPTU+ 0x0034))
-#define IFXMIPS_GPTU_GPT_T2_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 3 Register***/
-#define IFXMIPS_GPTU_GPT_T3                       ((volatile u32*)(IFXMIPS_GPTU+ 0x0038))
-#define IFXMIPS_GPTU_GPT_T3_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Register***/
-#define IFXMIPS_GPTU_GPT_T4                       ((volatile u32*)(IFXMIPS_GPTU+ 0x003C))
-#define IFXMIPS_GPTU_GPT_T4_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 5 Register***/
-#define IFXMIPS_GPTU_GPT_T5                       ((volatile u32*)(IFXMIPS_GPTU+ 0x0040))
-#define IFXMIPS_GPTU_GPT_T5_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Register***/
-#define IFXMIPS_GPTU_GPT_T6                       ((volatile u32*)(IFXMIPS_GPTU+ 0x0044))
-#define IFXMIPS_GPTU_GPT_T6_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Control Register***/
-#define IFXMIPS_GPTU_GPT_T6CON                    ((volatile u32*)(IFXMIPS_GPTU+ 0x0020))
-#define IFXMIPS_GPTU_GPT_T6CON_T6SR                            (1 << 15)
-#define IFXMIPS_GPTU_GPT_T6CON_T6CLR                          (1 << 14)
-#define IFXMIPS_GPTU_GPT_T6CON_BPS2 (value)               (((( 1 << 2) - 1) & (value)) << 11)
-#define IFXMIPS_GPTU_GPT_T6CON_T6OTL                          (1 << 10)
-#define IFXMIPS_GPTU_GPT_T6CON_T6UD                            (1 << 7)
-#define IFXMIPS_GPTU_GPT_T6CON_T6R                              (1 << 6)
-#define IFXMIPS_GPTU_GPT_T6CON_T6M (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define IFXMIPS_GPTU_GPT_T6CON_T6I (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 6 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define IFXMIPS_GPTU_GPT_WHBT6CON                 ((volatile u32*)(IFXMIPS_GPTU+ 0x0054))
-#define IFXMIPS_GPTU_GPT_WHBT6CON_SETT6OTL                  (1 << 11)
-#define IFXMIPS_GPTU_GPT_WHBT6CON_CLRT6OTL                  (1 << 10)
-
-/***GPT Timer 5 Control Register***/
-#define IFXMIPS_GPTU_GPT_T5CON                    ((volatile u32*)(IFXMIPS_GPTU+ 0x001C))
-#define IFXMIPS_GPTU_GPT_T5CON_T5SC                            (1 << 15)
-#define IFXMIPS_GPTU_GPT_T5CON_T5CLR                          (1 << 14)
-#define IFXMIPS_GPTU_GPT_T5CON_CI (value)                (((( 1 << 2) - 1) & (value)) << 12)
-#define IFXMIPS_GPTU_GPT_T5CON_T5CC                            (1 << 11)
-#define IFXMIPS_GPTU_GPT_T5CON_CT3                              (1 << 10)
-#define IFXMIPS_GPTU_GPT_T5CON_T5RC                            (1 << 9)
-#define IFXMIPS_GPTU_GPT_T5CON_T5UDE                          (1 << 8)
-#define IFXMIPS_GPTU_GPT_T5CON_T5UD                            (1 << 7)
-#define IFXMIPS_GPTU_GPT_T5CON_T5R                              (1 << 6)
-#define IFXMIPS_GPTU_GPT_T5CON_T5M (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define IFXMIPS_GPTU_GPT_T5CON_T5I (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  IOM register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_IOM                          (0xBF105000)
-/***********************************************************************/
-
-/***Receive FIFO***/
-#define IFXMIPS_IOM_RFIFO                        ((volatile u32*)(IFXMIPS_IOM+ 0x0000))
-#define IFXMIPS_IOM_RFIFO_RXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Transmit FIFO***/
-#define IFXMIPS_IOM_XFIFO                        ((volatile u32*)(IFXMIPS_IOM+ 0x0000))
-#define IFXMIPS_IOM_XFIFO_TXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Interrupt Status Register HDLC***/
-#define IFXMIPS_IOM_ISTAH                        ((volatile u32*)(IFXMIPS_IOM+ 0x0080))
-#define IFXMIPS_IOM_ISTAH_RME                              (1 << 7)
-#define IFXMIPS_IOM_ISTAH_RPF                              (1 << 6)
-#define IFXMIPS_IOM_ISTAH_RFO                              (1 << 5)
-#define IFXMIPS_IOM_ISTAH_XPR                              (1 << 4)
-#define IFXMIPS_IOM_ISTAH_XMR                              (1 << 3)
-#define IFXMIPS_IOM_ISTAH_XDU                              (1 << 2)
-
-/***Interrupt Mask Register HDLC***/
-#define IFXMIPS_IOM_MASKH                        ((volatile u32*)(IFXMIPS_IOM+ 0x0080))
-#define IFXMIPS_IOM_MASKH_RME                              (1 << 7)
-#define IFXMIPS_IOM_MASKH_RPF                              (1 << 6)
-#define IFXMIPS_IOM_MASKH_RFO                              (1 << 5)
-#define IFXMIPS_IOM_MASKH_XPR                              (1 << 4)
-#define IFXMIPS_IOM_MASKH_XMR                              (1 << 3)
-#define IFXMIPS_IOM_MASKH_XDU                              (1 << 2)
-
-/***Status Register***/
-#define IFXMIPS_IOM_STAR                         ((volatile u32*)(IFXMIPS_IOM+ 0x0084))
-#define IFXMIPS_IOM_STAR_XDOV                            (1 << 7)
-#define IFXMIPS_IOM_STAR_XFW                              (1 << 6)
-#define IFXMIPS_IOM_STAR_RACI                            (1 << 3)
-#define IFXMIPS_IOM_STAR_XACI                            (1 << 1)
-
-/***Command Register***/
-#define IFXMIPS_IOM_CMDR                         ((volatile u32*)(IFXMIPS_IOM+ 0x0084))
-#define IFXMIPS_IOM_CMDR_RMC                              (1 << 7)
-#define IFXMIPS_IOM_CMDR_RRES                            (1 << 6)
-#define IFXMIPS_IOM_CMDR_XTF                              (1 << 3)
-#define IFXMIPS_IOM_CMDR_XME                              (1 << 1)
-#define IFXMIPS_IOM_CMDR_XRES                            (1 << 0)
-
-/***Mode Register***/
-#define IFXMIPS_IOM_MODEH                        ((volatile u32*)(IFXMIPS_IOM+ 0x0088))
-#define IFXMIPS_IOM_MODEH_MDS2                            (1 << 7)
-#define IFXMIPS_IOM_MODEH_MDS1                            (1 << 6)
-#define IFXMIPS_IOM_MODEH_MDS0                            (1 << 5)
-#define IFXMIPS_IOM_MODEH_RAC                              (1 << 3)
-#define IFXMIPS_IOM_MODEH_DIM2                            (1 << 2)
-#define IFXMIPS_IOM_MODEH_DIM1                            (1 << 1)
-#define IFXMIPS_IOM_MODEH_DIM0                            (1 << 0)
-
-/***Extended Mode Register***/
-#define IFXMIPS_IOM_EXMR                         ((volatile u32*)(IFXMIPS_IOM+ 0x008C))
-#define IFXMIPS_IOM_EXMR_XFBS                            (1 << 7)
-#define IFXMIPS_IOM_EXMR_RFBS (value)               (((( 1 << 2) - 1) & (value)) << 5)
-#define IFXMIPS_IOM_EXMR_SRA                              (1 << 4)
-#define IFXMIPS_IOM_EXMR_XCRC                            (1 << 3)
-#define IFXMIPS_IOM_EXMR_RCRC                            (1 << 2)
-#define IFXMIPS_IOM_EXMR_ITF                              (1 << 0)
-
-/***SAPI1 Register***/
-#define IFXMIPS_IOM_SAP1                         ((volatile u32*)(IFXMIPS_IOM+ 0x0094))
-#define IFXMIPS_IOM_SAP1_SAPI1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-#define IFXMIPS_IOM_SAP1_MHA                              (1 << 0)
-
-/***Receive Frame Byte Count Low***/
-#define IFXMIPS_IOM_RBCL                         ((volatile u32*)(IFXMIPS_IOM+ 0x0098))
-#define IFXMIPS_IOM_RBCL_RBC(value)              (1 << value)
-
-/***SAPI2 Register***/
-#define IFXMIPS_IOM_SAP2                         ((volatile u32*)(IFXMIPS_IOM+ 0x0098))
-#define IFXMIPS_IOM_SAP2_SAPI2 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-#define IFXMIPS_IOM_SAP2_MLA                              (1 << 0)
-
-/***Receive Frame Byte Count High***/
-#define IFXMIPS_IOM_RBCH                         ((volatile u32*)(IFXMIPS_IOM+ 0x009C))
-#define IFXMIPS_IOM_RBCH_OV                              (1 << 4)
-#define IFXMIPS_IOM_RBCH_RBC11                          (1 << 3)
-#define IFXMIPS_IOM_RBCH_RBC10                          (1 << 2)
-#define IFXMIPS_IOM_RBCH_RBC9                            (1 << 1)
-#define IFXMIPS_IOM_RBCH_RBC8                            (1 << 0)
-
-/***TEI1 Register 1***/
-#define IFXMIPS_IOM_TEI1                         ((volatile u32*)(IFXMIPS_IOM+ 0x009C))
-#define IFXMIPS_IOM_TEI1_TEI1 (value)               (((( 1 << 7) - 1) & (value)) << 1)
-#define IFXMIPS_IOM_TEI1_EA                              (1 << 0)
-
-/***Receive Status Register***/
-#define IFXMIPS_IOM_RSTA                         ((volatile u32*)(IFXMIPS_IOM+ 0x00A0))
-#define IFXMIPS_IOM_RSTA_VFR                              (1 << 7)
-#define IFXMIPS_IOM_RSTA_RDO                              (1 << 6)
-#define IFXMIPS_IOM_RSTA_CRC                              (1 << 5)
-#define IFXMIPS_IOM_RSTA_RAB                              (1 << 4)
-#define IFXMIPS_IOM_RSTA_SA1                              (1 << 3)
-#define IFXMIPS_IOM_RSTA_SA0                              (1 << 2)
-#define IFXMIPS_IOM_RSTA_TA                              (1 << 0)
-#define IFXMIPS_IOM_RSTA_CR                              (1 << 1)
-
-/***TEI2 Register***/
-#define IFXMIPS_IOM_TEI2                         ((volatile u32*)(IFXMIPS_IOM+ 0x00A0))
-#define IFXMIPS_IOM_TEI2_TEI2 (value)               (((( 1 << 7) - 1) & (value)) << 1)
-#define IFXMIPS_IOM_TEI2_EA                              (1 << 0)
-
-/***Test Mode Register HDLC***/
-#define IFXMIPS_IOM_TMH                          ((volatile u32*)(IFXMIPS_IOM+ 0x00A4))
-#define IFXMIPS_IOM_TMH_TLP                              (1 << 0)
-
-/***Command/Indication Receive 0***/
-#define IFXMIPS_IOM_CIR0                         ((volatile u32*)(IFXMIPS_IOM+ 0x00B8))
-#define IFXMIPS_IOM_CIR0_CODR0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_IOM_CIR0_CIC0                            (1 << 3)
-#define IFXMIPS_IOM_CIR0_CIC1                            (1 << 2)
-#define IFXMIPS_IOM_CIR0_SG                              (1 << 1)
-#define IFXMIPS_IOM_CIR0_BAS                              (1 << 0)
-
-/***Command/Indication Transmit 0***/
-#define IFXMIPS_IOM_CIX0                         ((volatile u32*)(IFXMIPS_IOM+ 0x00B8))
-#define IFXMIPS_IOM_CIX0_CODX0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
-#define IFXMIPS_IOM_CIX0_TBA2                            (1 << 3)
-#define IFXMIPS_IOM_CIX0_TBA1                            (1 << 2)
-#define IFXMIPS_IOM_CIX0_TBA0                            (1 << 1)
-#define IFXMIPS_IOM_CIX0_BAC                              (1 << 0)
-
-/***Command/Indication Receive 1***/
-#define IFXMIPS_IOM_CIR1                         ((volatile u32*)(IFXMIPS_IOM+ 0x00BC))
-#define IFXMIPS_IOM_CIR1_CODR1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-
-/***Command/Indication Transmit 1***/
-#define IFXMIPS_IOM_CIX1                         ((volatile u32*)(IFXMIPS_IOM+ 0x00BC))
-#define IFXMIPS_IOM_CIX1_CODX1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-#define IFXMIPS_IOM_CIX1_CICW                            (1 << 1)
-#define IFXMIPS_IOM_CIX1_CI1E                            (1 << 0)
-
-/***Controller Data Access Reg. (CH10)***/
-#define IFXMIPS_IOM_CDA10                        ((volatile u32*)(IFXMIPS_IOM+ 0x0100))
-#define IFXMIPS_IOM_CDA10_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH11)***/
-#define IFXMIPS_IOM_CDA11                        ((volatile u32*)(IFXMIPS_IOM+ 0x0104))
-#define IFXMIPS_IOM_CDA11_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH20)***/
-#define IFXMIPS_IOM_CDA20                        ((volatile u32*)(IFXMIPS_IOM+ 0x0108))
-#define IFXMIPS_IOM_CDA20_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH21)***/
-#define IFXMIPS_IOM_CDA21                        ((volatile u32*)(IFXMIPS_IOM+ 0x010C))
-#define IFXMIPS_IOM_CDA21_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define IFXMIPS_IOM_CDA_TSDP10                   ((volatile u32*)(IFXMIPS_IOM+ 0x0110))
-#define IFXMIPS_IOM_CDA_TSDP10_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CDA_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define IFXMIPS_IOM_CDA_TSDP11                   ((volatile u32*)(IFXMIPS_IOM+ 0x0114))
-#define IFXMIPS_IOM_CDA_TSDP11_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CDA_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define IFXMIPS_IOM_CDA_TSDP20                   ((volatile u32*)(IFXMIPS_IOM+ 0x0118))
-#define IFXMIPS_IOM_CDA_TSDP20_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CDA_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define IFXMIPS_IOM_CDA_TSDP21                   ((volatile u32*)(IFXMIPS_IOM+ 0x011C))
-#define IFXMIPS_IOM_CDA_TSDP21_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CDA_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define IFXMIPS_IOM_CO_TSDP10                    ((volatile u32*)(IFXMIPS_IOM+ 0x0120))
-#define IFXMIPS_IOM_CO_TSDP10_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CO_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define IFXMIPS_IOM_CO_TSDP11                    ((volatile u32*)(IFXMIPS_IOM+ 0x0124))
-#define IFXMIPS_IOM_CO_TSDP11_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CO_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define IFXMIPS_IOM_CO_TSDP20                    ((volatile u32*)(IFXMIPS_IOM+ 0x0128))
-#define IFXMIPS_IOM_CO_TSDP20_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CO_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define IFXMIPS_IOM_CO_TSDP21                    ((volatile u32*)(IFXMIPS_IOM+ 0x012C))
-#define IFXMIPS_IOM_CO_TSDP21_DPS                              (1 << 7)
-#define IFXMIPS_IOM_CO_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define IFXMIPS_IOM_CDA1_CR                      ((volatile u32*)(IFXMIPS_IOM+ 0x0138))
-#define IFXMIPS_IOM_CDA1_CR_EN_TBM                        (1 << 5)
-#define IFXMIPS_IOM_CDA1_CR_EN_I1                          (1 << 4)
-#define IFXMIPS_IOM_CDA1_CR_EN_I0                          (1 << 3)
-#define IFXMIPS_IOM_CDA1_CR_EN_O1                          (1 << 2)
-#define IFXMIPS_IOM_CDA1_CR_EN_O0                          (1 << 1)
-#define IFXMIPS_IOM_CDA1_CR_SWAP                            (1 << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define IFXMIPS_IOM_CDA2_CR                      ((volatile u32*)(IFXMIPS_IOM+ 0x013C))
-#define IFXMIPS_IOM_CDA2_CR_EN_TBM                        (1 << 5)
-#define IFXMIPS_IOM_CDA2_CR_EN_I1                          (1 << 4)
-#define IFXMIPS_IOM_CDA2_CR_EN_I0                          (1 << 3)
-#define IFXMIPS_IOM_CDA2_CR_EN_O1                          (1 << 2)
-#define IFXMIPS_IOM_CDA2_CR_EN_O0                          (1 << 1)
-#define IFXMIPS_IOM_CDA2_CR_SWAP                            (1 << 0)
-
-/***Control Register B-Channel Data***/
-#define IFXMIPS_IOM_BCHA_CR                      ((volatile u32*)(IFXMIPS_IOM+ 0x0144))
-#define IFXMIPS_IOM_BCHA_CR_EN_BC2                        (1 << 4)
-#define IFXMIPS_IOM_BCHA_CR_EN_BC1                        (1 << 3)
-
-/***Control Register B-Channel Data***/
-#define IFXMIPS_IOM_BCHB_CR                      ((volatile u32*)(IFXMIPS_IOM+ 0x0148))
-#define IFXMIPS_IOM_BCHB_CR_EN_BC2                        (1 << 4)
-#define IFXMIPS_IOM_BCHB_CR_EN_BC1                        (1 << 3)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define IFXMIPS_IOM_DCI_CR                       ((volatile u32*)(IFXMIPS_IOM+ 0x014C))
-#define IFXMIPS_IOM_DCI_CR_DPS_CI1                      (1 << 7)
-#define IFXMIPS_IOM_DCI_CR_EN_CI1                        (1 << 6)
-#define IFXMIPS_IOM_DCI_CR_EN_D                            (1 << 5)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define IFXMIPS_IOM_DCIC_CR                      ((volatile u32*)(IFXMIPS_IOM+ 0x014C))
-#define IFXMIPS_IOM_DCIC_CR_DPS_CI0                      (1 << 7)
-#define IFXMIPS_IOM_DCIC_CR_EN_CI0                        (1 << 6)
-#define IFXMIPS_IOM_DCIC_CR_DPS_D                          (1 << 5)
-
-/***Control Reg. Serial Data Strobe x***/
-#define IFXMIPS_IOM_SDS_CR                       ((volatile u32*)(IFXMIPS_IOM+ 0x0154))
-#define IFXMIPS_IOM_SDS_CR_ENS_TSS                      (1 << 7)
-#define IFXMIPS_IOM_SDS_CR_ENS_TSS_1                  (1 << 6)
-#define IFXMIPS_IOM_SDS_CR_ENS_TSS_3                  (1 << 5)
-#define IFXMIPS_IOM_SDS_CR_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Control Register IOM Data***/
-#define IFXMIPS_IOM_IOM_CR                       ((volatile u32*)(IFXMIPS_IOM+ 0x015C))
-#define IFXMIPS_IOM_IOM_CR_SPU                              (1 << 7)
-#define IFXMIPS_IOM_IOM_CR_CI_CS                          (1 << 5)
-#define IFXMIPS_IOM_IOM_CR_TIC_DIS                      (1 << 4)
-#define IFXMIPS_IOM_IOM_CR_EN_BCL                        (1 << 3)
-#define IFXMIPS_IOM_IOM_CR_CLKM                            (1 << 2)
-#define IFXMIPS_IOM_IOM_CR_Res                              (1 << 1)
-#define IFXMIPS_IOM_IOM_CR_DIS_IOM                      (1 << 0)
-
-/***Synchronous Transfer Interrupt***/
-#define IFXMIPS_IOM_STI                          ((volatile u32*)(IFXMIPS_IOM+ 0x0160))
-#define IFXMIPS_IOM_STI_STOV21                        (1 << 7)
-#define IFXMIPS_IOM_STI_STOV20                        (1 << 6)
-#define IFXMIPS_IOM_STI_STOV11                        (1 << 5)
-#define IFXMIPS_IOM_STI_STOV10                        (1 << 4)
-#define IFXMIPS_IOM_STI_STI21                          (1 << 3)
-#define IFXMIPS_IOM_STI_STI20                          (1 << 2)
-#define IFXMIPS_IOM_STI_STI11                          (1 << 1)
-#define IFXMIPS_IOM_STI_STI10                          (1 << 0)
-
-/***Acknowledge Synchronous Transfer Interrupt***/
-#define IFXMIPS_IOM_ASTI                         ((volatile u32*)(IFXMIPS_IOM+ 0x0160))
-#define IFXMIPS_IOM_ASTI_ACK21                          (1 << 3)
-#define IFXMIPS_IOM_ASTI_ACK20                          (1 << 2)
-#define IFXMIPS_IOM_ASTI_ACK11                          (1 << 1)
-#define IFXMIPS_IOM_ASTI_ACK10                          (1 << 0)
-
-/***Mask Synchronous Transfer Interrupt***/
-#define IFXMIPS_IOM_MSTI                         ((volatile u32*)(IFXMIPS_IOM+ 0x0164))
-#define IFXMIPS_IOM_MSTI_STOV21                        (1 << 7)
-#define IFXMIPS_IOM_MSTI_STOV20                        (1 << 6)
-#define IFXMIPS_IOM_MSTI_STOV11                        (1 << 5)
-#define IFXMIPS_IOM_MSTI_STOV10                        (1 << 4)
-#define IFXMIPS_IOM_MSTI_STI21                          (1 << 3)
-#define IFXMIPS_IOM_MSTI_STI20                          (1 << 2)
-#define IFXMIPS_IOM_MSTI_STI11                          (1 << 1)
-#define IFXMIPS_IOM_MSTI_STI10                          (1 << 0)
-
-/***Configuration Register for Serial Data Strobes***/
-#define IFXMIPS_IOM_SDS_CONF                    ((volatile u32*)(IFXMIPS_IOM+ 0x0168))
-#define IFXMIPS_IOM_SDS_CONF_SDS_BCL                      (1 << 0)
-
-/***Monitoring CDA Bits***/
-#define IFXMIPS_IOM_MCDA                         ((volatile u32*)(IFXMIPS_IOM+ 0x016C))
-#define IFXMIPS_IOM_MCDA_MCDA21 (value)             (((( 1 << 2) - 1) & (value)) << 6)
-#define IFXMIPS_IOM_MCDA_MCDA20 (value)             (((( 1 << 2) - 1) & (value)) << 4)
-#define IFXMIPS_IOM_MCDA_MCDA11 (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define IFXMIPS_IOM_MCDA_MCDA10 (value)             (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  ASC0 register address and bits                      */
-/***********************************************************************/
-#define IFXMIPS_ASC0                          (KSEG1+0x1E100400)
-/***********************************************************************/
-#define IFXMIPS_ASC0_TBUF                        ((volatile u32*)(IFXMIPS_ASC0 + 0x0020))
-#define IFXMIPS_ASC0_RBUF                        ((volatile u32*)(IFXMIPS_ASC0 + 0x0024))
-#define IFXMIPS_ASC0_FSTAT                       ((volatile u32*)(IFXMIPS_ASC0 + 0x0048))
-#define IFXMIPS_ASC0_FSTAT_TXFREE_GET(value)     (((value) >> 24) & ((1 << 6) - 1))
-#define IFXMIPS_ASC0_FSTAT_TXFREE_SET(value)     (((( 1 << 6) - 1) & (value)) << 24)
-#define IFXMIPS_ASC0_FSTAT_RXFREE_GET(value)     (((value) >> 16) & ((1 << 6) - 1))
-#define IFXMIPS_ASC0_FSTAT_RXFREE_SET(value)     (((( 1 << 6) - 1) & (value)) << 16)
-#define IFXMIPS_ASC0_FSTAT_TXFFL_GET(value)      (((value) >> 8) & ((1 << 6) - 1))
-#define IFXMIPS_ASC0_FSTAT_TXFFL_SET(value)      (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_ASC0_FSTAT_RXFFL_GET(value)      (((value) >> 0) & ((1 << 6) - 1))
-#define IFXMIPS_ASC0_FSTAT_RXFFL_SET(value)      (((( 1 << 6) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  ASC1 register address and bits                      */
-/***********************************************************************/
-
-#define IFXMIPS_ASC1                          (KSEG1+0x1E100C00)
-/***********************************************************************/
-/***ASC Clock Control Register***/
-#define IFXMIPS_ASC1_CLC                      ((volatile u32*)(IFXMIPS_ASC1+ 0x0000))
-#define IFXMIPS_ASC1_CLC_RMC(value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define IFXMIPS_ASC1_CLC_DISS                            (1 << 1)
-#define IFXMIPS_ASC1_CLC_DISR                            (1 << 0)
-
-/***ASC Port Input Select Register***/
-#define IFXMIPS_ASC1_PISEL                    ((volatile u32*)(IFXMIPS_ASC1+ 0x0004))
-#define IFXMIPS_ASC1_PISEL                    ((volatile u32*)(IFXMIPS_ASC1+ 0x0004))
-#define IFXMIPS_ASC1_PISEL_RIS                              (1 << 0)
-
-/***ASC Control Register***/
-#define IFXMIPS_ASC1_CON                      ((volatile u32*)(IFXMIPS_ASC1+ 0x0010))
-#define IFXMIPS_ASC1_CON_BEN                              (1 << 20)
-#define IFXMIPS_ASC1_CON_TOEN                              (1 << 20)
-#define IFXMIPS_ASC1_CON_ROEN                              (1 << 19)
-#define IFXMIPS_ASC1_CON_RUEN                              (1 << 18)
-#define IFXMIPS_ASC1_CON_FEN                              (1 << 17)
-#define IFXMIPS_ASC1_CON_PAL                              (1 << 16)
-#define IFXMIPS_ASC1_CON_R                              (1 << 15)
-#define IFXMIPS_ASC1_CON_ACO                             (1 << 14)
-#define IFXMIPS_ASC1_CON_LB                              (1 << 13)
-#define IFXMIPS_ASC1_CON_ERCLK                             (1 << 10)
-#define IFXMIPS_ASC1_CON_FDE                              (1 << 9)
-#define IFXMIPS_ASC1_CON_BRS                              (1 << 8)
-#define IFXMIPS_ASC1_CON_STP                              (1 << 7)
-#define IFXMIPS_ASC1_CON_SP                              (1 << 6)
-#define IFXMIPS_ASC1_CON_ODD                              (1 << 5)
-#define IFXMIPS_ASC1_CON_PEN                              (1 << 4)
-#define IFXMIPS_ASC1_CON_M(value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***ASC Staus Register***/
-#define IFXMIPS_ASC1_STATE                      ((volatile u32*)(IFXMIPS_ASC1+ 0x0014))
-/***ASC Write Hardware Modified Control Register***/
-#define IFXMIPS_ASC1_WHBSTATE                   ((volatile u32*)(IFXMIPS_ASC1+ 0x0018))
-#define IFXMIPS_ASC1_WHBSTATE_SETBE                          (1 << 113)
-#define IFXMIPS_ASC1_WHBSTATE_SETTOE                          (1 << 12)
-#define IFXMIPS_ASC1_WHBSTATE_SETROE                          (1 << 11)
-#define IFXMIPS_ASC1_WHBSTATE_SETRUE                          (1 << 10)
-#define IFXMIPS_ASC1_WHBSTATE_SETFE                          (1 << 19)
-#define IFXMIPS_ASC1_WHBSTATE_SETPE                          (1 << 18)
-#define IFXMIPS_ASC1_WHBSTATE_CLRBE                          (1 << 17)
-#define IFXMIPS_ASC1_WHBSTATE_CLRTOE                          (1 << 6)
-#define IFXMIPS_ASC1_WHBSTATE_CLRROE                          (1 << 5)
-#define IFXMIPS_ASC1_WHBSTATE_CLRRUE                          (1 << 4)
-#define IFXMIPS_ASC1_WHBSTATE_CLRFE                          (1 << 3)
-#define IFXMIPS_ASC1_WHBSTATE_CLRPE                          (1 << 2)
-#define IFXMIPS_ASC1_WHBSTATE_SETREN                        (1 << 1)
-#define IFXMIPS_ASC1_WHBSTATE_CLRREN                        (1 << 0)
-
-/***ASC Baudrate Timer/Reload Register***/
-#define IFXMIPS_ASC1_BG                      ((volatile u32*)(IFXMIPS_ASC1+ 0x0050))
-#define IFXMIPS_ASC1_BG_BR_VALUE(value)          (((( 1 << 13) - 1) & (value)) << 0)
-
-/***ASC Fractional Divider Register***/
-#define IFXMIPS_ASC1_FDV                      ((volatile u32*)(IFXMIPS_ASC1+ 0x0018))
-#define IFXMIPS_ASC1_FDV_FD_VALUE(value)          (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Transmit Buffer Register***/
-#define IFXMIPS_ASC1_TBUF                    ((volatile u32*)(IFXMIPS_ASC1+ 0x0020))
-#define IFXMIPS_ASC1_TBUF_TD_VALUE(value)          (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Receive Buffer Register***/
-#define IFXMIPS_ASC1_RBUF                    ((volatile u32*)(IFXMIPS_ASC1+ 0x0024))
-#define IFXMIPS_ASC1_RBUF_RD_VALUE(value)          (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Autobaud Control Register***/
-#define IFXMIPS_ASC1_ABCON                    ((volatile u32*)(IFXMIPS_ASC1+ 0x0030))
-#define IFXMIPS_ASC1_ABCON_RXINV                          (1 << 11)
-#define IFXMIPS_ASC1_ABCON_TXINV                          (1 << 10)
-#define IFXMIPS_ASC1_ABCON_ABEM(value)               (((( 1 << 2) - 1) & (value)) << 8)
-#define IFXMIPS_ASC1_ABCON_FCDETEN                      (1 << 4)
-#define IFXMIPS_ASC1_ABCON_ABDETEN                      (1 << 3)
-#define IFXMIPS_ASC1_ABCON_ABSTEN                        (1 << 2)
-#define IFXMIPS_ASC1_ABCON_AUREN                          (1 << 1)
-#define IFXMIPS_ASC1_ABCON_ABEN                            (1 << 0)
-
-/***Receive FIFO Control Register***/
-#define IFXMIPS_ASC1_RXFCON                       ((volatile u32*)(IFXMIPS_ASC1+ 0x0040))
-#define IFXMIPS_ASC1_RXFCON_RXFITL(value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_ASC1_RXFCON_RXFFLU                        (1 << 1)
-#define IFXMIPS_ASC1_RXFCON_RXFEN                          (1 << 0)
-
-/***Transmit FIFO Control Register***/
-#define IFXMIPS_ASC1_TXFCON                       ((volatile u32*)(IFXMIPS_ASC1+ 0x0044))
-#define IFXMIPS_ASC1_TXFCON_TXFITL(value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_ASC1_TXFCON_TXFFLU                        (1 << 1)
-#define IFXMIPS_ASC1_TXFCON_TXFEN                          (1 << 0)
-
-/***FIFO Status Register***/
-#define IFXMIPS_ASC1_FSTAT                        ((volatile u32*)(IFXMIPS_ASC1+ 0x0048))
-#define IFXMIPS_ASC1_FSTAT_TXFFL(value)              (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_ASC1_FSTAT_RXFFL(value)              (((( 1 << 6) - 1) & (value)) << 0)
-#define IFXMIPS_ASC1_FSTAT_TXFREE_GET(value)     (((value) >> 24) & ((1 << 6) - 1))
-#define IFXMIPS_ASC1_FSTAT_TXFREE_SET(value)     (((( 1 << 6) - 1) & (value)) << 24)
-#define IFXMIPS_ASC1_FSTAT_RXFREE_GET(value)     (((value) >> 16) & ((1 << 6) - 1))
-#define IFXMIPS_ASC1_FSTAT_RXFREE_SET(value)     (((( 1 << 6) - 1) & (value)) << 16)
-#define IFXMIPS_ASC1_FSTAT_TXFFL_GET(value)      (((value) >> 8) & ((1 << 6) - 1))
-#define IFXMIPS_ASC1_FSTAT_TXFFL_SET(value)      (((( 1 << 6) - 1) & (value)) << 8)
-#define IFXMIPS_ASC1_FSTAT_RXFFL_GET(value)      (((value) >> 0) & ((1 << 6) - 1))
-#define IFXMIPS_ASC1_FSTAT_RXFFL_SET(value)      (((( 1 << 6) - 1) & (value)) << 0)
-
-/***ASC Autobaud Status Register***/
-#define IFXMIPS_ASC1_ABSTAT                   ((volatile u32*)(IFXMIPS_ASC1+ 0x0034))
-#define IFXMIPS_ASC1_ABSTAT_DETWAIT                      (1 << 4)
-#define IFXMIPS_ASC1_ABSTAT_SCCDET                        (1 << 3)
-#define IFXMIPS_ASC1_ABSTAT_SCSDET                        (1 << 2)
-#define IFXMIPS_ASC1_ABSTAT_FCCDET                        (1 << 1)
-#define IFXMIPS_ASC1_ABSTAT_FCSDET                        (1 << 0)
-
-/***ASC Write HW Modified Autobaud Status Register***/
-#define IFXMIPS_ASC1_WHBABSTAT                 ((volatile u32*)(IFXMIPS_ASC1+ 0x003C))
-#define IFXMIPS_ASC1_WHBABSTAT_SETDETWAIT                (1 << 9)
-#define IFXMIPS_ASC1_WHBABSTAT_CLRDETWAIT                (1 << 8)
-#define IFXMIPS_ASC1_WHBABSTAT_SETSCCDET                  (1 << 7)
-#define IFXMIPS_ASC1_WHBABSTAT_CLRSCCDET                  (1 << 6)
-#define IFXMIPS_ASC1_WHBABSTAT_SETSCSDET                  (1 << 5)
-#define IFXMIPS_ASC1_WHBABSTAT_CLRSCSDET                  (1 << 4)
-#define IFXMIPS_ASC1_WHBABSTAT_SETFCCDET                  (1 << 3)
-#define IFXMIPS_ASC1_WHBABSTAT_CLRFCCDET                  (1 << 2)
-#define IFXMIPS_ASC1_WHBABSTAT_SETFCSDET                  (1 << 1)
-#define IFXMIPS_ASC1_WHBABSTAT_CLRFCSDET                  (1 << 0)
-
-/***ASC IRNCR0 **/
-#define IFXMIPS_ASC1_IRNREN                    ((volatile u32*)(IFXMIPS_ASC1+ 0x00F4))
-#define IFXMIPS_ASC1_IRNICR                    ((volatile u32*)(IFXMIPS_ASC1+ 0x00FC))
-/***ASC IRNCR1 **/
-#define IFXMIPS_ASC1_IRNCR                     ((volatile u32*)(IFXMIPS_ASC1+ 0x00F8))
-#define ASC_IRNCR_TIR  0x4
-#define ASC_IRNCR_RIR  0x2
-#define ASC_IRNCR_EIR  0x4
-
-/***********************************************************************/
-/*  Module      :  DMA register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_DMA                          (0xBE104100)
-/***********************************************************************/
-
-#define IFXMIPS_DMA_BASE                 IFXMIPS_DMA
-#define IFXMIPS_DMA_CLC                  (volatile u32*)IFXMIPS_DMA_BASE
-#define IFXMIPS_DMA_ID                   (volatile u32*)(IFXMIPS_DMA_BASE+0x08)
-#define IFXMIPS_DMA_CTRL                 (volatile u32*)(IFXMIPS_DMA_BASE+0x10)
-#define IFXMIPS_DMA_CPOLL                (volatile u32*)(IFXMIPS_DMA_BASE+0x14)
-#define IFXMIPS_DMA_CS                   (volatile u32*)(IFXMIPS_DMA_BASE+0x18)
-#define IFXMIPS_DMA_CCTRL                (volatile u32*)(IFXMIPS_DMA_BASE+0x1C)
-#define IFXMIPS_DMA_CDBA                 (volatile u32*)(IFXMIPS_DMA_BASE+0x20)
-#define IFXMIPS_DMA_CDLEN                (volatile u32*)(IFXMIPS_DMA_BASE+0x24)
-#define IFXMIPS_DMA_CIS                  (volatile u32*)(IFXMIPS_DMA_BASE+0x28)
-#define IFXMIPS_DMA_CIE                  (volatile u32*)(IFXMIPS_DMA_BASE+0x2C)
-
-#define IFXMIPS_DMA_PS                   (volatile u32*)(IFXMIPS_DMA_BASE+0x40)
-#define IFXMIPS_DMA_PCTRL                (volatile u32*)(IFXMIPS_DMA_BASE+0x44)
-
-#define IFXMIPS_DMA_IRNEN                (volatile u32*)(IFXMIPS_DMA_BASE+0xf4)
-#define IFXMIPS_DMA_IRNCR                (volatile u32*)(IFXMIPS_DMA_BASE+0xf8)
-#define IFXMIPS_DMA_IRNICR               (volatile u32*)(IFXMIPS_DMA_BASE+0xfc)
-/***********************************************************************/
-/*  Module      :  Debug register address and bits                     */
-/***********************************************************************/
-
-#define IFXMIPS_Debug                        (0xBF106000)
-/***********************************************************************/
-
-/***MCD Break Bus Switch Register***/
-#define IFXMIPS_Debug_MCD_BBS                      ((volatile u32*)(IFXMIPS_Debug+ 0x0000))
-#define IFXMIPS_Debug_MCD_BBS_BTP1                            (1 << 19)
-#define IFXMIPS_Debug_MCD_BBS_BTP0                            (1 << 18)
-#define IFXMIPS_Debug_MCD_BBS_BSP1                            (1 << 17)
-#define IFXMIPS_Debug_MCD_BBS_BSP0                            (1 << 16)
-#define IFXMIPS_Debug_MCD_BBS_BT5EN                          (1 << 15)
-#define IFXMIPS_Debug_MCD_BBS_BT4EN                          (1 << 14)
-#define IFXMIPS_Debug_MCD_BBS_BT5                              (1 << 13)
-#define IFXMIPS_Debug_MCD_BBS_BT4                              (1 << 12)
-#define IFXMIPS_Debug_MCD_BBS_BS5EN                          (1 << 7)
-#define IFXMIPS_Debug_MCD_BBS_BS4EN                          (1 << 6)
-#define IFXMIPS_Debug_MCD_BBS_BS5                              (1 << 5)
-#define IFXMIPS_Debug_MCD_BBS_BS4                              (1 << 4)
-
-/***MCD Multiplexer Control Register***/
-#define IFXMIPS_Debug_MCD_MCR                      ((volatile u32*)(IFXMIPS_Debug+ 0x0008))
-#define IFXMIPS_Debug_MCD_MCR_MUX5                            (1 << 4)
-#define IFXMIPS_Debug_MCD_MCR_MUX4                            (1 << 3)
-#define IFXMIPS_Debug_MCD_MCR_MUX1                            (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  SRAM register address and bits                      */
-/***********************************************************************/
-
-#define IFXMIPS_SRAM                         (0xBF980000)
-/***********************************************************************/
-
-/***SRAM Size Register***/
-#define IFXMIPS_SRAM_SRAM_SIZE                    ((volatile u32*)(IFXMIPS_SRAM+ 0x0800))
-#define IFXMIPS_SRAM_SRAM_SIZE_SIZE (value)               (((( 1 << 23) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  BIU register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_BIU                          (0xBFA80000)
-/***********************************************************************/
-
-/***BIU Identification Register***/
-#define IFXMIPS_BIU_BIU_ID                       ((volatile u32*)(IFXMIPS_BIU+ 0x0000))
-#define IFXMIPS_BIU_BIU_ID_ARCH                            (1 << 16)
-#define IFXMIPS_BIU_BIU_ID_ID (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define IFXMIPS_BIU_BIU_ID_REV (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***BIU Access Error Cause Register***/
-#define IFXMIPS_BIU_BIU_ERRCAUSE                 ((volatile u32*)(IFXMIPS_BIU+ 0x0100))
-#define IFXMIPS_BIU_BIU_ERRCAUSE_ERR                              (1 << 31)
-#define IFXMIPS_BIU_BIU_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define IFXMIPS_BIU_BIU_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***BIU Access Error Address Register***/
-#define IFXMIPS_BIU_BIU_ERRADDR                  ((volatile u32*)(IFXMIPS_BIU+ 0x0108))
-#define IFXMIPS_BIU_BIU_ERRADDR_ADDR
-
-/***********************************************************************/
-/*  Module      :  ICU register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_ICU                          (0xBF880200)
-/***********************************************************************/
-#define IFXMIPS_ICU_IM0_ISR                      ((volatile u32*)(IFXMIPS_ICU + 0x0000))
-#define IFXMIPS_ICU_IM0_IER                      ((volatile u32*)(IFXMIPS_ICU + 0x0008))
-#define IFXMIPS_ICU_IM0_IOSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0010))
-#define IFXMIPS_ICU_IM0_IRSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0018))
-#define IFXMIPS_ICU_IM0_IMR                      ((volatile u32*)(IFXMIPS_ICU + 0x0020))
-#define IFXMIPS_ICU_IM0_IMR_IID                  (1 << 31)
-#define IFXMIPS_ICU_IM0_IMR_IN_GET(value)        (((value) >> 0) & ((1 << 5) - 1))
-#define IFXMIPS_ICU_IM0_IMR_IN_SET(value)        (((( 1 << 5) - 1) & (value)) << 0)
-#define IFXMIPS_ICU_IM0_IR(value)                (1 << (value))
-
-#define IFXMIPS_ICU_IM1_ISR                      ((volatile u32*)(IFXMIPS_ICU + 0x0028))
-#define IFXMIPS_ICU_IM1_IER                      ((volatile u32*)(IFXMIPS_ICU + 0x0030))
-#define IFXMIPS_ICU_IM1_IOSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0038))
-#define IFXMIPS_ICU_IM1_IRSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0040))
-#define IFXMIPS_ICU_IM1_IMR                      ((volatile u32*)(IFXMIPS_ICU + 0x0048))
-#define IFXMIPS_ICU_IM1_IMR_IID                  (1 << 31)
-#define IFXMIPS_ICU_IM1_IMR_IN_GET(value)        (((value) >> 0) & ((1 << 5) - 1))
-#define IFXMIPS_ICU_IM1_IMR_IN_SET(value)        (((( 1 << 5) - 1) & (value)) << 0)
-#define IFXMIPS_ICU_IM1_IR(value)                (1 << (value))
-
-#define IFXMIPS_ICU_IM2_ISR                      ((volatile u32*)(IFXMIPS_ICU + 0x0050))
-#define IFXMIPS_ICU_IM2_IER                      ((volatile u32*)(IFXMIPS_ICU + 0x0058))
-#define IFXMIPS_ICU_IM2_IOSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0060))
-#define IFXMIPS_ICU_IM2_IRSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0068))
-#define IFXMIPS_ICU_IM2_IMR                      ((volatile u32*)(IFXMIPS_ICU + 0x0070))
-#define IFXMIPS_ICU_IM2_IMR_IID                  (1 << 31)
-#define IFXMIPS_ICU_IM2_IMR_IN_GET(value)        (((value) >> 0) & ((1 << 5) - 1))
-#define IFXMIPS_ICU_IM2_IMR_IN_SET(value)        (((( 1 << 5) - 1) & (value)) << 0)
-#define IFXMIPS_ICU_IM2_IR(value)                (1 << (value))
-
-#define IFXMIPS_ICU_IM3_ISR                      ((volatile u32*)(IFXMIPS_ICU + 0x0078))
-#define IFXMIPS_ICU_IM3_IER                      ((volatile u32*)(IFXMIPS_ICU + 0x0080))
-#define IFXMIPS_ICU_IM3_IOSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0088))
-#define IFXMIPS_ICU_IM3_IRSR                     ((volatile u32*)(IFXMIPS_ICU + 0x0090))
-#define IFXMIPS_ICU_IM3_IMR                      ((volatile u32*)(IFXMIPS_ICU + 0x0098))
-#define IFXMIPS_ICU_IM3_IMR_IID                  (1 << 31)
-#define IFXMIPS_ICU_IM3_IMR_IN_GET(value)        (((value) >> 0) & ((1 << 5) - 1))
-#define IFXMIPS_ICU_IM3_IMR_IN_SET(value)        (((( 1 << 5) - 1) & (value)) << 0)
-#define IFXMIPS_ICU_IM3_IR(value)                (1 << (value))
-
-#define IFXMIPS_ICU_IM4_ISR                      ((volatile u32*)(IFXMIPS_ICU + 0x00A0))
-#define IFXMIPS_ICU_IM4_IER                      ((volatile u32*)(IFXMIPS_ICU + 0x00A8))
-#define IFXMIPS_ICU_IM4_IOSR                     ((volatile u32*)(IFXMIPS_ICU + 0x00B0))
-#define IFXMIPS_ICU_IM4_IRSR                     ((volatile u32*)(IFXMIPS_ICU + 0x00B8))
-#define IFXMIPS_ICU_IM4_IMR                      ((volatile u32*)(IFXMIPS_ICU + 0x00C0))
-#define IFXMIPS_ICU_IM4_IMR_IID                  (1 << 31)
-#define IFXMIPS_ICU_IM4_IMR_IN_GET(value)        (((value) >> 0) & ((1 << 5) - 1))
-#define IFXMIPS_ICU_IM4_IMR_IN_SET(value)        (((( 1 << 5) - 1) & (value)) << 0)
-#define IFXMIPS_ICU_IM4_IR(value)                (1 << (value))
-
-#define IFXMIPS_ICU_IM5_ISR                      ((volatile u32*)(IFXMIPS_ICU + 0x00C8))
-#define IFXMIPS_ICU_IM5_IER                      ((volatile u32*)(IFXMIPS_ICU + 0x00D0))
-#define IFXMIPS_ICU_IM5_IOSR                     ((volatile u32*)(IFXMIPS_ICU + 0x00D8))
-#define IFXMIPS_ICU_IM5_IRSR                     ((volatile u32*)(IFXMIPS_ICU + 0x00E0))
-#define IFXMIPS_ICU_IM5_IMR                      ((volatile u32*)(IFXMIPS_ICU + 0x00E8))
-#define IFXMIPS_ICU_IM5_IMR_IID                  (1 << 31)
-#define IFXMIPS_ICU_IM5_IMR_IN_GET(value)        (((value) >> 0) & ((1 << 5) - 1))
-#define IFXMIPS_ICU_IM5_IMR_IN_SET(value)        (((( 1 << 5) - 1) & (value)) << 0)
-#define IFXMIPS_ICU_IM5_IR(value)                (1 << (value))
-
-/***Interrupt Vector Value Register***/
-//#define IFXMIPS_ICU_IM_VEC                      ((volatile u32*)(IFXMIPS_ICU+ 0x00f0))
-#define IFXMIPS_ICU_IM_VEC                      ((volatile u32*)(IFXMIPS_ICU+ 0x00EC))
-
-/***Interrupt Vector Value Mask***/
-#define IFXMIPS_ICU_IM0_VEC_MASK                0x0000001f
-#define IFXMIPS_ICU_IM1_VEC_MASK                0x000003e0
-#define IFXMIPS_ICU_IM2_VEC_MASK                0x00007c00
-#define IFXMIPS_ICU_IM3_VEC_MASK                0x000f8000
-#define IFXMIPS_ICU_IM4_VEC_MASK                0x01f00000
-
-#define IFXMIPS_ICU_IM0_ISR_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM0_IER_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM1_ISR_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM1_IER_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM2_ISR_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM2_IER_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM3_ISR_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM3_IER_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM4_ISR_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM4_IER_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM5_ISR_IR(value)          (1<<(value))
-#define IFXMIPS_ICU_IM5_IER_IR(value)          (1<<(value))
-
-/***DMA Interrupt Mask Value***/
-#define IFXMIPS_DMA_H_MASK                     0x00000fff
-
-/***External Interrupt Control Register***/
-#define IFXMIPS_ICU_EIU                    (KSEG1+0x1f101000)
-#define IFXMIPS_ICU_EIU_EXIN_C                ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x0000))
-#define IFXMIPS_ICU_EIU_INIC                  ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x0004))
-#define IFXMIPS_ICU_EIU_INC                   ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x0008))
-#define IFXMIPS_ICU_EIU_INEN                   ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x000c))
-
-/***********************************************************************/
-/*  Module      :  MPS register address and bits                       */
-/***********************************************************************/
-
-#define IFXMIPS_MPS                          (KSEG1+0x1F107000)
-/***********************************************************************/
-
-#define IFXMIPS_MPS_CHIPID                       ((volatile u32*)(IFXMIPS_MPS + 0x0344))
-#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)    (((value) >> 28) & ((1 << 4) - 1))
-#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)    (((( 1 << 4) - 1) & (value)) << 28)
-#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)    (((value) >> 12) & ((1 << 16) - 1))
-#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)    (((( 1 << 16) - 1) & (value)) << 12)
-#define IFXMIPS_MPS_CHIPID_MANID_GET(value)      (((value) >> 1) & ((1 << 10) - 1))
-#define IFXMIPS_MPS_CHIPID_MANID_SET(value)      (((( 1 << 10) - 1) & (value)) << 1)
-
-/* voice channel 0 ... 3 interrupt enable register */
-#define IFXMIPS_MPS_VC0ENR ((volatile u32*)(IFXMIPS_MPS + 0x0000))
-#define IFXMIPS_MPS_VC1ENR ((volatile u32*)(IFXMIPS_MPS + 0x0004))
-#define IFXMIPS_MPS_VC2ENR ((volatile u32*)(IFXMIPS_MPS + 0x0008))
-#define IFXMIPS_MPS_VC3ENR ((volatile u32*)(IFXMIPS_MPS + 0x000C))
-/* voice channel 0 ... 3 interrupt status read register */
-#define IFXMIPS_MPS_RVC0SR ((volatile u32*)(IFXMIPS_MPS + 0x0010))
-#define IFXMIPS_MPS_RVC1SR ((volatile u32*)(IFXMIPS_MPS + 0x0014))
-#define IFXMIPS_MPS_RVC2SR ((volatile u32*)(IFXMIPS_MPS + 0x0018))
-#define IFXMIPS_MPS_RVC3SR ((volatile u32*)(IFXMIPS_MPS + 0x001C))
-/* voice channel 0 ... 3 interrupt status set register */
-#define IFXMIPS_MPS_SVC0SR ((volatile u32*)(IFXMIPS_MPS + 0x0020))
-#define IFXMIPS_MPS_SVC1SR ((volatile u32*)(IFXMIPS_MPS + 0x0024))
-#define IFXMIPS_MPS_SVC2SR ((volatile u32*)(IFXMIPS_MPS + 0x0028))
-#define IFXMIPS_MPS_SVC3SR ((volatile u32*)(IFXMIPS_MPS + 0x002C))
-/* voice channel 0 ... 3 interrupt status clear register */
-#define IFXMIPS_MPS_CVC0SR ((volatile u32*)(IFXMIPS_MPS + 0x0030))
-#define IFXMIPS_MPS_CVC1SR ((volatile u32*)(IFXMIPS_MPS + 0x0034))
-#define IFXMIPS_MPS_CVC2SR ((volatile u32*)(IFXMIPS_MPS + 0x0038))
-#define IFXMIPS_MPS_CVC3SR ((volatile u32*)(IFXMIPS_MPS + 0x003C))
-/* common status 0 and 1 read register */
-#define IFXMIPS_MPS_RAD0SR ((volatile u32*)(IFXMIPS_MPS + 0x0040))
-#define IFXMIPS_MPS_RAD1SR ((volatile u32*)(IFXMIPS_MPS + 0x0044))
-/* common status 0 and 1 set register */
-#define IFXMIPS_MPS_SAD0SR ((volatile u32*)(IFXMIPS_MPS + 0x0048))
-#define IFXMIPS_MPS_SAD1SR ((volatile u32*)(IFXMIPS_MPS + 0x004C))
-/* common status 0 and 1 clear register */
-#define IFXMIPS_MPS_CAD0SR ((volatile u32*)(IFXMIPS_MPS + 0x0050))
-#define IFXMIPS_MPS_CAD1SR ((volatile u32*)(IFXMIPS_MPS + 0x0054))
-/* common status 0 and 1 enable register */
-#define IFXMIPS_MPS_AD0ENR ((volatile u32*)(IFXMIPS_MPS + 0x0058))
-#define IFXMIPS_MPS_AD1ENR ((volatile u32*)(IFXMIPS_MPS + 0x005C))
-/* notification enable register */
-#define IFXMIPS_MPS_CPU0_NFER ((volatile u32*)(IFXMIPS_MPS + 0x0060))
-#define IFXMIPS_MPS_CPU1_NFER ((volatile u32*)(IFXMIPS_MPS + 0x0064))
-/* CPU to CPU interrup request register */
-#define IFXMIPS_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFXMIPS_MPS + 0x0070))
-#define IFXMIPS_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFXMIPS_MPS + 0x0074))
-/* Global interrupt request and request enable register */
-#define IFXMIPS_MPS_GIRR ((volatile u32*)(IFXMIPS_MPS + 0x0078))
-#define IFXMIPS_MPS_GIER ((volatile u32*)(IFXMIPS_MPS + 0x007C))
-
-#define IFXMIPS_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000))
-
-#define IFXMIPS_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0))
-
-#define IFXMIPS_FUSE_BASE_ADDR (KSEG1+0x1F107354)
-
-/************************************************************************/
-/*   Module       :   DEU register address and bits                    */
-/************************************************************************/
-//#define IFXMIPS_DEU_BASE_ADDR               (0xBE102000)
-#define IFXMIPS_DEU_BASE_ADDR               (KSEG1 + 0x1E103100)
-/*   DEU Control Register */
-#define IFXMIPS_DEU_CLK                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0000))
-#define IFXMIPS_DEU_ID                      ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0008))
-
-/*   DEU control register */
-#define IFXMIPS_DES_CON                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0010))
-#define IFXMIPS_DES_IHR                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0014))
-#define IFXMIPS_DES_ILR                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0018))
-#define IFXMIPS_DES_K1HR                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x001C))
-#define IFXMIPS_DES_K1LR                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0020))
-#define IFXMIPS_DES_K3HR                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0024))
-#define IFXMIPS_DES_K3LR                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0028))
-#define IFXMIPS_DES_IVHR                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x002C))
-#define IFXMIPS_DES_IVLR                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0030))
-#define IFXMIPS_DES_OHR                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0040))
-#define IFXMIPS_DES_OLR                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0050))
-
-/* AES DEU register */
-#define IFXMIPS_AES_CON                           ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0050))
-#define IFXMIPS_AES_ID3R                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0054))
-#define IFXMIPS_AES_ID2R                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0058))
-#define IFXMIPS_AES_ID1R                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x005C))
-#define IFXMIPS_AES_ID0R                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0060))
-
-/* AES Key register */
-#define IFXMIPS_AES_K7R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0064))
-#define IFXMIPS_AES_K6R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0068))
-#define IFXMIPS_AES_K5R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x006C))
-#define IFXMIPS_AES_K4R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0070))
-#define IFXMIPS_AES_K3R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0074))
-#define IFXMIPS_AES_K2R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0078))
-#define IFXMIPS_AES_K1R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x007C))
-#define IFXMIPS_AES_K0R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0080))
-
-/* AES vector register */
-#define IFXMIPS_AES_IV3R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0084))
-#define IFXMIPS_AES_IV2R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0088))
-#define IFXMIPS_AES_IV1R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x008C))
-#define IFXMIPS_AES_IV0R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0090))
-#define IFXMIPS_AES_0D3R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0094))
-#define IFXMIPS_AES_0D2R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0098))
-#define IFXMIPS_AES_OD1R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x009C))
-#define IFXMIPS_AES_OD0R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00A0))
-
-/* hash control registe */
-#define IFXMIPS_HASH_CON                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00B0))
-#define IFXMIPS_HASH_MR                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00B4))
-#define IFXMIPS_HASH_D1R                    ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00B8 ))
-#define IFXMIPS_HASH_D2R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00BC ))
-#define IFXMIPS_HASH_D3R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00C0 ))
-#define IFXMIPS_HASH_D4R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00C4))
-#define IFXMIPS_HASH_D5R                     ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00C8))
-
-#define IFXMIPS_CON                         ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00EC))
-
-#define IFXMIPS_DEU_IRNEN                         ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00F4))
-#define IFXMIPS_DEU_IRNCR                         ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00F8))
-#define IFXMIPS_DEU_IRNICR                         ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00FC))
-
-/************************************************************************/
-/*   Module       :   PPE register address and bits                    */
-/************************************************************************/
-#define IFXMIPS_PPE32_BASE  0xBE180000
-#define IFXMIPS_PPE32_DEBUG_BREAK_TRACE_REG   (IFXMIPS_PPE32_BASE + (0x0000 * 4))
-#define IFXMIPS_PPE32_INT_MASK_STATUS_REG     (IFXMIPS_PPE32_BASE + (0x0030 * 4))
-#define IFXMIPS_PPE32_INT_RESOURCE_REG        (IFXMIPS_PPE32_BASE + (0x0040 * 4))
-#define IFXMIPS_PPE32_CDM_CODE_MEM_B0         (IFXMIPS_PPE32_BASE + (0x1000 * 4))
-#define IFXMIPS_PPE32_CDM_CODE_MEM_B1         (IFXMIPS_PPE32_BASE + (0x2000 * 4))
-#define IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE   (IFXMIPS_PPE32_BASE + (0x4000 * 4))
-
-#define IFXMIPS_PPE32_SRST                  (IFXMIPS_PPE32_BASE + 0x10080)
-
-/*
- *    ETOP MDIO Registers
- */
-#define IFXMIPS_PPE32_ETOP_MDIO_CFG           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
-#define IFXMIPS_PPE32_ETOP_MDIO_ACC           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
-#define IFXMIPS_PPE32_ETOP_CFG                ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
-#define IFXMIPS_PPE32_ETOP_IG_VLAN_COS        ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
-#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS3       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
-#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS2       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
-#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS1       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
-#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS0       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
-#define IFXMIPS_PPE32_ETOP_IG_PLEN_CTRL       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
-#define IFXMIPS_PPE32_ETOP_ISR                ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
-#define IFXMIPS_PPE32_ETOP_IER                ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
-#define IFXMIPS_PPE32_ETOP_VPID               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
-
-/* ENET Register */
-#define IFXMIPS_PPE32_ENET_MAC_CFG             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
-#define IFXMIPS_PPE32_ENET_IG_PKTDROP                  ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
-#define IFXMIPS_PPE32_ENET_CoS_CFG             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
-
-/* Sharebuff SB RAM2 control data */
-
-#define IFXMIPS_PPE32_SB2_DATABASE     ((IFXMIPS_PPE32_BASE + (0x8C00 * 4)))
-#define IFXMIPS_PPE32_SB2_CTRLBASE     ((IFXMIPS_PPE32_BASE + (0x92E0 * 4)))
-/************************************************************************/
-/*   Module       :   PPE register address and bits                    */
-/************************************************************************/
-#define IFXMIPS_PPE32_BASE  0xBE180000
-#define IFXMIPS_PPE32_DEBUG_BREAK_TRACE_REG   (IFXMIPS_PPE32_BASE + (0x0000 * 4))
-#define IFXMIPS_PPE32_INT_MASK_STATUS_REG     (IFXMIPS_PPE32_BASE + (0x0030 * 4))
-#define IFXMIPS_PPE32_INT_RESOURCE_REG        (IFXMIPS_PPE32_BASE + (0x0040 * 4))
-#define IFXMIPS_PPE32_CDM_CODE_MEM_B0         (IFXMIPS_PPE32_BASE + (0x1000 * 4))
-#define IFXMIPS_PPE32_CDM_CODE_MEM_B1         (IFXMIPS_PPE32_BASE + (0x2000 * 4))
-#define IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE   (IFXMIPS_PPE32_BASE + (0x4000 * 4))
-
-/*
- *    ETOP MDIO Registers
- */
-#define ETOP_MDIO_CFG           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
-#define ETOP_MDIO_ACC           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
-#define ETOP_CFG                ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
-#define ETOP_IG_VLAN_COS        ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
-#define ETOP_IG_DSCP_COS3       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
-#define ETOP_IG_DSCP_COS2       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
-#define ETOP_IG_DSCP_COS1       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
-#define ETOP_IG_DSCP_COS0       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
-#define ETOP_IG_PLEN_CTRL       ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
-#define ETOP_ISR                ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
-#define ETOP_IER                ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
-#define ETOP_VPID               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
-#define ENET_MAC_CFG            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
-#define ENETS_DBA               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
-#define ENETS_CBA               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
-#define ENETS_CFG               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
-#define ENETS_PGCNT             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
-#define ENETS_PKTCNT            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
-#define ENETS_BUF_CTRL          ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
-#define ENETS_COS_CFG           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
-#define ENETS_IGDROP            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
-#define ENETS_IGERR             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
-#define ENET_MAC_DA0           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
-#define ENET_MAC_DA1           ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
-
-#define ENETF_DBA               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4)))
-#define ENETF_CBA               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4)))
-#define ENETF_CFG               ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4)))
-#define ENETF_PGCNT             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4)))
-#define ENETF_PKTCNT            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4)))
-#define ENETF_HFCTRL            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4)))
-#define ENETF_TXCTRL            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4)))
-
-#define ENETF_VLCOS0            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4)))
-#define ENETF_VLCOS1            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4)))
-#define ENETF_VLCOS2            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4)))
-#define ENETF_VLCOS3            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4)))
-#define ENETF_EGERR             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4)))
-#define ENETF_EGDROP            ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4)))
-
-/* ENET Register */
-#define IFXMIPS_PPE32_ENET_MAC_CFG             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
-#define IFXMIPS_PPE32_ENET_IG_PKTDROP                  ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
-#define IFXMIPS_PPE32_ENET_CoS_CFG             ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
-
-/* Sharebuff SB RAM2 control data */
-
-#define IFXMIPS_PPE32_SB2_DATABASE     ((IFXMIPS_PPE32_BASE + (0x8C00 * 4)))
-#define IFXMIPS_PPE32_SB2_CTRLBASE     ((IFXMIPS_PPE32_BASE + (0x92E0 * 4)))
-
-/***********************************************************************/
-/*  Module      :  PCI register address and bits                       */
-/***********************************************************************/
-#define PCI_CR_PR_OFFSET            (KSEG1+0x1E105400)
-#define PCI_CFG_BASE                         (KSEG1+0x17000000)
-#define PCI_MEM_BASE                         (KSEG1+0x18000000)
-#define PCI_CS_PR_OFFSET            (KSEG1+0x17000000)
-
-/* PCI CONTROLLER REGISTER ADDRESS MAP */
-#define PCI_CR_CLK_CTRL_REG         (PCI_CR_PR_OFFSET + 0x0000)
-#define PCI_CR_PCI_ID_REG              (PCI_CR_PR_OFFSET + 0x0004)
-#define PCI_CR_SFT_RST_REG             (PCI_CR_PR_OFFSET + 0x0010)
-#define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014)
-#define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018)
-#define PCI_CR_FPI_ERR_TAG_REG     (PCI_CR_PR_OFFSET + 0x001C)
-#define PCI_CR_PCI_IRR_REG             (PCI_CR_PR_OFFSET + 0x0020)
-#define PCI_CR_PCI_IRA_REG             (PCI_CR_PR_OFFSET + 0x0024)
-#define PCI_CR_PCI_IRM_REG             (PCI_CR_PR_OFFSET + 0x0028)
-#define PCI_CR_PCI_EOI_REG             (PCI_CR_PR_OFFSET + 0x002C)
-#define PCI_CR_PCI_MOD_REG             (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CR_DV_ID_REG               (PCI_CR_PR_OFFSET + 0x0034)
-#define PCI_CR_SUBSYS_ID_REG       (PCI_CR_PR_OFFSET + 0x0038)
-#define PCI_CR_PCI_PM_REG           (PCI_CR_PR_OFFSET + 0x003C)
-#define PCI_CR_CLASS_CODE1_REG      (PCI_CR_PR_OFFSET + 0x0040)
-#define PCI_CR_BAR11MASK_REG       (PCI_CR_PR_OFFSET + 0x0044)
-#define PCI_CR_BAR12MASK_REG        (PCI_CR_PR_OFFSET + 0x0048)
-#define PCI_CR_BAR13MASK_REG        (PCI_CR_PR_OFFSET + 0x004C)
-#define PCI_CR_BAR14MASK_REG        (PCI_CR_PR_OFFSET + 0x0050)
-#define PCI_CR_BAR15MASK_REG        (PCI_CR_PR_OFFSET + 0x0054)
-#define PCI_CR_BAR16MASK_REG        (PCI_CR_PR_OFFSET + 0x0058)
-#define PCI_CR_CIS_PT1_REG             (PCI_CR_PR_OFFSET + 0x005C)
-#define PCI_CR_SUBSYS_ID1_REG      (PCI_CR_PR_OFFSET + 0x0060)
-#define PCI_CR_PCI_ADDR_MAP11_REG   (PCI_CR_PR_OFFSET + 0x0064)
-#define PCI_CR_PCI_ADDR_MAP12_REG   (PCI_CR_PR_OFFSET + 0x0068)
-#define PCI_CR_PCI_ADDR_MAP13_REG   (PCI_CR_PR_OFFSET + 0x006C)
-#define PCI_CR_PCI_ADDR_MAP14_REG   (PCI_CR_PR_OFFSET + 0x0070)
-#define PCI_CR_PCI_ADDR_MAP15_REG   (PCI_CR_PR_OFFSET + 0x0074)
-#define PCI_CR_PCI_ADDR_MAP16_REG   (PCI_CR_PR_OFFSET + 0x0078)
-#define PCI_CR_FPI_SEG_EN_REG       (PCI_CR_PR_OFFSET + 0x007C)
-#define PCI_CR_PC_ARB_REG              (PCI_CR_PR_OFFSET + 0x0080)
-#define PCI_CR_BAR21MASK_REG       (PCI_CR_PR_OFFSET + 0x0084)
-#define PCI_CR_BAR22MASK_REG        (PCI_CR_PR_OFFSET + 0x0088)
-#define PCI_CR_BAR23MASK_REG        (PCI_CR_PR_OFFSET + 0x008C)
-#define PCI_CR_BAR24MASK_REG        (PCI_CR_PR_OFFSET + 0x0090)
-#define PCI_CR_BAR25MASK_REG        (PCI_CR_PR_OFFSET + 0x0094)
-#define PCI_CR_BAR26MASK_REG        (PCI_CR_PR_OFFSET + 0x0098)
-#define PCI_CR_CIS_PT2_REG             (PCI_CR_PR_OFFSET + 0x009C)
-#define PCI_CR_SUBSYS_ID2_REG      (PCI_CR_PR_OFFSET + 0x00A0)
-#define PCI_CR_PCI_ADDR_MAP21_REG   (PCI_CR_PR_OFFSET + 0x00A4)
-#define PCI_CR_PCI_ADDR_MAP22_REG   (PCI_CR_PR_OFFSET + 0x00A8)
-#define PCI_CR_PCI_ADDR_MAP23_REG   (PCI_CR_PR_OFFSET + 0x00AC)
-#define PCI_CR_PCI_ADDR_MAP24_REG   (PCI_CR_PR_OFFSET + 0x00B0)
-#define PCI_CR_PCI_ADDR_MAP25_REG   (PCI_CR_PR_OFFSET + 0x00B4)
-#define PCI_CR_PCI_ADDR_MAP26_REG   (PCI_CR_PR_OFFSET + 0x00B8)
-#define PCI_CR_FPI_ADDR_MASK_REG    (PCI_CR_PR_OFFSET + 0x00BC)
-#define PCI_CR_FCI_ADDR_MAP0_REG    (PCI_CR_PR_OFFSET + 0x00C0)
-#define PCI_CR_FCI_ADDR_MAP1_REG    (PCI_CR_PR_OFFSET + 0x00C4)
-#define PCI_CR_FCI_ADDR_MAP2_REG    (PCI_CR_PR_OFFSET + 0x00C8)
-#define PCI_CR_FCI_ADDR_MAP3_REG    (PCI_CR_PR_OFFSET + 0x00CC)
-#define PCI_CR_FCI_ADDR_MAP4_REG    (PCI_CR_PR_OFFSET + 0x00D0)
-#define PCI_CR_FCI_ADDR_MAP5_REG    (PCI_CR_PR_OFFSET + 0x00D4)
-#define PCI_CR_FCI_ADDR_MAP6_REG    (PCI_CR_PR_OFFSET + 0x00D8)
-#define PCI_CR_FCI_ADDR_MAP7_REG    (PCI_CR_PR_OFFSET + 0x00DC)
-#define PCI_CR_FCI_ADDR_MAP11lo_REG (PCI_CR_PR_OFFSET + 0x00E0)
-#define PCI_CR_FCI_ADDR_MAP11hg_REG (PCI_CR_PR_OFFSET + 0x00E4)
-#define PCI_CR_FCI_BURST_LENGTH_REG (PCI_CR_PR_OFFSET + 0x00E8)
-#define PCI_CR_PCI_SET_SERR_REG     (PCI_CR_PR_OFFSET + 0x00EC)
-#define PCI_CR_DMA_FPI_ST_ADDR_REG  (PCI_CR_PR_OFFSET + 0x00F0)
-#define PCI_CR_DMA_PCI_ST_ADDR_REG  (PCI_CR_PR_OFFSET + 0x00F4)
-#define PCI_CR_DMA_TRAN_CNT_REG     (PCI_CR_PR_OFFSET + 0x00F8)
-#define PCI_CR_DMA_TRAN_CTL_REG     (PCI_CR_PR_OFFSET + 0x00FC)
-
-/* PCI CONFIGURATION SPACE REGISTER Base Address */
-#define EXT_PCI1_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x0800
-#define EXT_PCI2_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x1000
-#define EXT_PCI3_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x1800
-#define EXT_PCI4_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x2000
-#define EXT_PCI5_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x2800
-#define EXT_PCI6_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x3000
-#define EXT_PCI7_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x3800
-#define EXT_PCI8_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x4000
-#define EXT_PCI9_CONFIG_SPACE_BASE_ADDR        PCI_CFG_BASE + 0x4800
-#define EXT_PCI10_CONFIG_SPACE_BASE_ADDR       PCI_CFG_BASE + 0x5000
-#define EXT_PCI11_CONFIG_SPACE_BASE_ADDR       PCI_CFG_BASE + 0x5800
-#define EXT_PCI12_CONFIG_SPACE_BASE_ADDR       PCI_CFG_BASE + 0x6000
-#define EXT_PCI13_CONFIG_SPACE_BASE_ADDR       PCI_CFG_BASE + 0x6800
-#define EXT_PCI14_CONFIG_SPACE_BASE_ADDR       PCI_CFG_BASE + 0x7000
-#define EXT_PCI15_CONFIG_SPACE_BASE_ADDR       PCI_CFG_BASE + 0x7800
-#define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR     PCI_CFG_BASE + 0XF000
-
-/* PCI CONFIGURATION SPACE REGISTER ADDRESS MAP */
-#define PCI_CS_DEV_VEN_ID_REG        (PCI_CS_PR_OFFSET + 0x0000)
-#define PCI_CS_STS_CMD_REG              (PCI_CS_PR_OFFSET + 0x0004)
-#define PCI_CS_CL_CODE_REVIDG        (PCI_CS_PR_OFFSET + 0x0008)
-#define PCI_CS_BST_HT_LT_CLS_REG     (PCI_CS_PR_OFFSET + 0x000C)
-#define PCI_CS_BASE_ADDR1_REG       (PCI_CS_PR_OFFSET + 0x0010)
-#define PCI_CS_BASE_ADDR2_REG        (PCI_CS_PR_OFFSET + 0x0014)
-#define PCI_CS_BASE_ADDR3_REG        (PCI_CS_PR_OFFSET + 0x0018)
-#define PCI_CS_BASE_ADDR4_REG        (PCI_CS_PR_OFFSET + 0x001C)
-#define PCI_CS_BASE_ADDR5_REG        (PCI_CS_PR_OFFSET + 0x0020)
-#define PCI_CS_BASE_ADDR6_REG        (PCI_CS_PR_OFFSET + 0x0024)
-#define PCI_CS_CARDBUS_CIS_PT_REG    (PCI_CS_PR_OFFSET + 0x0028)
-#define PCI_CS_SUBSYS_VEN_ID_REG     (PCI_CS_PR_OFFSET + 0x002C)
-#define PCI_CS_EXROM_BAS_ADDR_REG    (PCI_CS_PR_OFFSET + 0x0030)
-#define PCI_CS_RES1_REG                     (PCI_CS_PR_OFFSET + 0x0034)
-#define PCI_CS_RES2_REG                     (PCI_CS_PR_OFFSET + 0x0038)
-#define PCI_CS_LAT_GNT_INTR_REG      (PCI_CS_PR_OFFSET + 0x003C)
-#define PCI_CS_PM_PT_CPID_REG        (PCI_CS_PR_OFFSET + 0x0040)
-#define PCI_CS_DAT_PMCSR_PM_REG             (PCI_CS_PR_OFFSET + 0x0044)
-#define PCI_CS_RES3_REG              (PCI_CS_PR_OFFSET + 0x0048)
-#define PCI_CS_RES4_REG              (PCI_CS_PR_OFFSET + 0x004C)
-#define PCI_CS_ERR_ADDR_PCI_FPI_REG  (PCI_CS_PR_OFFSET + 0x0050)
-#define PCI_CS_ERR_ADDR_FPI_PCI_REG  (PCI_CS_PR_OFFSET + 0x0054)
-#define PCI_CS_ERR_TAG_FPI_PCI_REG   (PCI_CS_PR_OFFSET + 0x0058)
-#define PCI_CS_PC_ARB_REG               (PCI_CS_PR_OFFSET + 0x005C)
-#define PCI_CS_FPI_PCI_INT_STS_REG   (PCI_CS_PR_OFFSET + 0x0060)
-#define PCI_CS_FPI_PCI_INT_ACK_REG   (PCI_CS_PR_OFFSET + 0x0064)
-#define PCI_CS_FPI_PCI_INT_MASK_REG  (PCI_CS_PR_OFFSET + 0x0068)
-#define PCI_CS_CARDBUS_CTL_STS_REG   (PCI_CS_PR_OFFSET + 0x006C)
-
-// PCI CONTROLLER ADDRESS SPACE
-#define PCI_CA_PR_OFFSET 0xB8000000
-#define PCI_CA_PR_END    0xBBFFFFFF
-
-// PCI CONTROLLER REGISTER ADDRESS MASK
-#define PCI_CR_CLK_CTRL_MSK              0x82000000
-#define PCI_CR_PCI_ID_MSK                   0x00000000
-#define PCI_CR_SFT_RST_MSK                  0x00000002
-#define PCI_CR_PCI_FPI_ERR_ADDR_MSK     0x00000000
-#define PCI_CR_FCI_PCI_ERR_ADDR_MSK     0x00000000
-#define PCI_CR_FPI_ERR_TAG_MSK          0x00000000
-#define PCI_CR_PCI_IRR_MSK                  0x07013B2F
-#define PCI_CR_PCI_IRA_MSK                  0x07013B2F
-#define PCI_CR_PCI_IRM_MSK                  0x07013B2F
-#define PCI_CR_PCI_EOI_MSK                  0x07013B2F
-#define PCI_CR_PCI_MOD_MSK                  0x1107070F
-#define PCI_CR_DV_ID_MSK                    0x00000000
-#define PCI_CR_SUBSYS_ID_MSK            0x00000000
-#define PCI_CR_PCI_PM_MSK               0x0000001F
-#define PCI_CR_CLASS_CODE1_MSK          0x00000000
-#define PCI_CR_BAR11MASK_MSK            0x8FFFFFF8
-#define PCI_CR_BAR12MASK_MSK            0x80001F08
-#define PCI_CR_BAR13MASK_MSK            0x8FF00008
-#define PCI_CR_BAR14MASK_MSK            0x8FFFFF08
-#define PCI_CR_BAR15MASK_MSK            0x8FFFFF08
-#define PCI_CR_BAR16MASK_MSK            0x8FFFFFF9
-#define PCI_CR_CIS_PT1_MSK                  0x03FFFFFF
-#define PCI_CR_SUBSYS_ID1_MSK           0x00000000
-#define PCI_CR_PCI_ADDR_MAP11_MSK       0x7FFF0001
-#define PCI_CR_PCI_ADDR_MAP12_MSK       0x7FFFFF01
-#define PCI_CR_PCI_ADDR_MAP13_MSK       0x7FF00001
-#define PCI_CR_PCI_ADDR_MAP14_MSK       0x7FFFFF01
-#define PCI_CR_PCI_ADDR_MAP15_MSK       0x7FF00001
-#define PCI_CR_PCI_ADDR_MAP16_MSK       0x7FF00001
-#define PCI_CR_FPI_SEG_EN_MSK           0x000003FF
-#define PCI_CR_CLASS_CODE2_MSK          0x00000000
-#define PCI_CR_BAR21MASK_MSK            0x800F0008
-#define PCI_CR_BAR22MASK_MSK            0x807F0008
-#define PCI_CR_BAR23MASK_MSK            0x8FF00008
-#define PCI_CR_BAR24MASK_MSK            0x8FFFFF08
-#define PCI_CR_BAR25MASK_MSK            0x8FFFFF08
-#define PCI_CR_BAR26MASK_MSK            0x8FFFFFF9
-#define PCI_CR_CIS_PT2_MSK                  0x03FFFFFF
-#define PCI_CR_SUBSYS_ID2_MSK           0x00000000
-#define PCI_CR_PCI_ADDR_MAP21_MSK       0x7FFE0001
-#define PCI_CR_PCI_ADDR_MAP22_MSK       0x7FFF0001
-#define PCI_CR_PCI_ADDR_MAP23_MSK       0x7FF00001
-#define PCI_CR_PCI_ADDR_MAP24_MSK       0x7FFFFF01
-#define PCI_CR_PCI_ADDR_MAP25_MSK       0x7FFFFF01
-#define PCI_CR_PCI_ADDR_MAP26_MSK       0x7FF00001
-#define PCI_CR_FPI_ADDR_MASK_MSK        0x00070000
-#define PCI_CR_FCI_ADDR_MAP0_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP1_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP2_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP3_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP4_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP5_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP6_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP7_MSK        0xFFF00000
-#define PCI_CR_FCI_ADDR_MAP11lo_MSK     0xFFFF0000
-#define PCI_CR_FCI_ADDR_MAP11hg_MSK     0xFFF00000
-#define PCI_CR_FCI_BURST_LENGTH_MSK     0x00000303
-#define PCI_CR_PCI_SET_SERR_MSK         0x00000001
-#define PCI_CR_DMA_FPI_ST_ADDR_MSK      0xFFFFFFFF
-#define PCI_CR_DMA_PCI_ST_ADDR_MSK      0xFFFFFFFF
-#define PCI_CR_DMA_TRAN_CNT_MSK         0x000003FF
-#define PCI_CR_DMA_TRAN_CTL_MSK         0x00000003
-
-#define INTERNAL_ARB_ENABLE_BIT                0
-#define ARB_SCHEME_BIT                         1
-#define PCI_MASTER0_PRIOR_2BITS                2
-#define PCI_MASTER1_PRIOR_2BITS                4
-#define PCI_MASTER2_PRIOR_2BITS                6
-#define PCI_MASTER0_REQ_MASK_2BITS             8
-#define PCI_MASTER1_REQ_MASK_2BITS             10
-#define PCI_MASTER2_REQ_MASK_2BITS             12
-
-#define IOPORT_RESOURCE_START 0x10000000
-#define IOPORT_RESOURCE_END   0xffffffff
-#define IOMEM_RESOURCE_START  0x10000000
-#define IOMEM_RESOURCE_END    0xffffffff
-
-/***********************************************************************/
-#define IFXMIPS_REG32(addr)               *((volatile u32 *)(addr))
-/***********************************************************************/
-#endif //IFXMIPS_H

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h
index 2b4af8b748a8ff02dc21be0cf0a7ba1ca885796e..b842734452719592158a6c7b849f5394d91d040a 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h
@@ -14,7 +14,6 @@
  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
  */
 #ifndef _IFXMIPS_PMU_H__
 #define _IFXMIPS_PMU_H__

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h
index 1c2013ed6d08bfae4adb33e1f4a8e1f37c5c47ac..822ff0bca6666530627fdde55dce83fc8d7a1c1c 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h
@@ -14,14 +14,13 @@
  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  *
  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org> 
- *
  */
-
 #ifndef _IFXPROM_H__
 #define _IFXPROM_H__
 
 extern void prom_printf(const char * fmt, ...);
 extern u32 *prom_get_cp1_base(void);
 extern u32 prom_get_cp1_size(void);
+extern int ifxmips_has_brn_block(void);
 
 #endif

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_serial.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_serial.h
deleted file mode 100644 (file)
index 87149a1..0000000
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_serial.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
-
-#ifndef __IFXMIPS_ASC_H
-#define __IFXMIPS_ASC_H
-
-/******************************************************************************
-**
-** FILE NAME    : serial.c
-** PROJECT      : IFXMips
-** MODULES      : ASC/UART
-**
-** DATE         : 27 MAR 2006
-** AUTHOR       : Liu Peng
-** DESCRIPTION  : Asynchronous Serial Channel (ASC/UART) Driver Header File
-** COPYRIGHT    :       Copyright (c) 2006
-**                      Infineon Technologies AG
-**                      Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-**    This program is free software; you can redistribute it and/or modify
-**    it under the terms of the GNU General Public License as published by
-**    the Free Software Foundation; either version 2 of the License, or
-**    (at your option) any later version.
-**
-** HISTORY
-** $Date        $Author         $Comment
-** 27 MAR 2006  Liu Peng        Initiate Version (rev 1.7)
-** 23 OCT 2006  Xu Liang        Add GPL header.
-*******************************************************************************/
-
-/* channel operating modes */
-/*#define      ASCOPT_CSIZE    0x00000003
-#define        ASCOPT_CS7      0x00000001
-#define        ASCOPT_CS8      0x00000002
-#define        ASCOPT_PARENB   0x00000004
-#define        ASCOPT_STOPB    0x00000008
-#define        ASCOPT_PARODD   0x00000010
-#define        ASCOPT_CREAD    0x00000020
-*/
-#define ASC_OPTIONS            (ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY    0
-
-#define IFXMIPSASC_TXFIFO_FL       1
-#define IFXMIPSASC_RXFIFO_FL       1
-#define IFXMIPSASC_TXFIFO_FULL     16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define IFXMIPSASC_IRQ_LINE_ALL        0x0000007f      /* all IRQs */
-
-#define IFXMIPSASC_IRQ_LINE_TIR            0x00000001  /* Tx Int */
-#define IFXMIPSASC_IRQ_LINE_TBIR           0x00000002  /* Tx Buffer Int */
-#define IFXMIPSASC_IRQ_LINE_RIR            0x00000004  /* Rx Int */
-#define IFXMIPSASC_IRQ_LINE_EIR            0x00000008  /* Error Int */
-#define IFXMIPSASC_IRQ_LINE_ABSTIR         0x00000010  /* Autobaud Start Int */
-#define IFXMIPSASC_IRQ_LINE_ABDETIP        0x00000020  /* Autobaud Detection Int */
-#define IFXMIPSASC_IRQ_LINE_SFCIR          0x00000040  /* Software Flow Control Int */
-
-/* interrupt controller access macros */
-#define ASC_INTERRUPTS_ENABLE(X)  \
-*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
-#define ASC_INTERRUPTS_DISABLE(X) \
-*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
-#define ASC_INTERRUPTS_CLEAR(X)   \
-*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR        0x00000001
-#define ASCCLC_DISS        0x00000002
-#define ASCCLC_RMCMASK     0x0000FF00
-#define ASCCLC_RMCOFFSET   8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK        0x0000000f
-#define ASCCON_M_8ASYNC        0x0
-#define ASCCON_M_8IRDA         0x1
-#define ASCCON_M_7ASYNC        0x2
-#define ASCCON_M_7IRDA         0x3
-#define ASCCON_WLSMASK         0x0000000c
-#define ASCCON_WLSOFFSET       2
-#define ASCCON_WLS_8BIT        0x0
-#define ASCCON_WLS_7BIT        0x1
-#define ASCCON_PEN             0x00000010
-#define ASCCON_ODD             0x00000020
-#define ASCCON_SP              0x00000040
-#define ASCCON_STP             0x00000080
-#define ASCCON_BRS             0x00000100
-#define ASCCON_FDE             0x00000200
-#define ASCCON_ERRCLK          0x00000400
-#define ASCCON_EMMASK          0x00001800
-#define ASCCON_EMOFFSET        11
-#define ASCCON_EM_ECHO_OFF     0x0
-#define ASCCON_EM_ECHO_AB      0x1
-#define ASCCON_EM_ECHO_ON      0x2
-#define ASCCON_LB              0x00002000
-#define ASCCON_ACO             0x00004000
-#define ASCCON_R               0x00008000
-#define ASCCON_PAL             0x00010000
-#define ASCCON_FEN             0x00020000
-#define ASCCON_RUEN            0x00040000
-#define ASCCON_ROEN            0x00080000
-#define ASCCON_TOEN            0x00100000
-#define ASCCON_BEN             0x00200000
-#define ASCCON_TXINV           0x01000000
-#define ASCCON_RXINV           0x02000000
-#define ASCCON_TXMSB           0x04000000
-#define ASCCON_RXMSB           0x08000000
-
-/* STATE register's bits and bitfields */
-#define ASCSTATE_REN           0x00000001
-#define ASCSTATE_PE            0x00010000
-#define ASCSTATE_FE            0x00020000
-#define ASCSTATE_RUE           0x00040000
-#define ASCSTATE_ROE           0x00080000
-#define ASCSTATE_TOE           0x00100000
-#define ASCSTATE_BE            0x00200000
-#define ASCSTATE_TXBVMASK      0x07000000
-#define ASCSTATE_TXBVOFFSET    24
-#define ASCSTATE_TXEOM         0x08000000
-#define ASCSTATE_RXBVMASK      0x70000000
-#define ASCSTATE_RXBVOFFSET    28
-#define ASCSTATE_RXEOM         0x80000000
-#define ASCSTATE_ANY   (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
-
-/* WHBSTATE register's bits and bitfields */
-#define ASCWHBSTATE_CLRREN    0x00000001
-#define ASCWHBSTATE_SETREN    0x00000002
-#define ASCWHBSTATE_CLRPE     0x00000004
-#define ASCWHBSTATE_CLRFE     0x00000008
-#define ASCWHBSTATE_CLRRUE    0x00000010
-#define ASCWHBSTATE_CLRROE    0x00000020
-#define ASCWHBSTATE_CLRTOE    0x00000040
-#define ASCWHBSTATE_CLRBE     0x00000080
-#define ASCWHBSTATE_SETPE     0x00000100
-#define ASCWHBSTATE_SETFE     0x00000200
-#define ASCWHBSTATE_SETRUE    0x00000400
-#define ASCWHBSTATE_SETROE    0x00000800
-#define ASCWHBSTATE_SETTOE    0x00001000
-#define ASCWHBSTATE_SETBE     0x00002000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN       0x0001
-#define ASCABCON_AUREN      0x0002
-#define ASCABCON_ABSTEN     0x0004
-#define ASCABCON_ABDETEN    0x0008
-#define ASCABCON_FCDETEN    0x0010
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK     0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_CLRABEN     0x0001
-#define ASCWHBABCON_SETABEN     0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET    0x0001
-#define ASCABSTAT_FCCDET    0x0002
-#define ASCABSTAT_SCSDET    0x0004
-#define ASCABSTAT_SCCDET    0x0008
-#define ASCABSTAT_DETWAIT   0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET  0x0001
-#define ASCWHBABSTAT_SETFCSDET  0x0002
-#define ASCWHBABSTAT_CLRFCCDET  0x0004
-#define ASCWHBABSTAT_SETFCCDET  0x0008
-#define ASCWHBABSTAT_CLRSCSDET  0x0010
-#define ASCWHBABSTAT_SETSCSDET  0x0020
-#define ASCWHBABSTAT_CLRSCCDET  0x0040
-#define ASCWHBABSTAT_SETSCCDET  0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFIFO1       0x00000400
-#define ASCTXFCON_TXFEN         0x0001
-#define ASCTXFCON_TXFFLU        0x0002
-#define ASCTXFCON_TXFITLMASK    0x3F00
-#define ASCTXFCON_TXFITLOFF     8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFIFO1       0x00000400
-#define ASCRXFCON_RXFEN         0x0001
-#define ASCRXFCON_RXFFLU        0x0002
-#define ASCRXFCON_RXFITLMASK    0x3F00
-#define ASCRXFCON_RXFITLOFF     8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK      0x003F
-#define ASCFSTAT_TXFFLMASK      0x3F00
-#define ASCFSTAT_TXFFLOFF       8
-
-#endif /* __IFXMIPS_ASC_H */