drm/msm/dsi: Add old timings quirk for 10nm phy

The v3.0.0 10nm phy has two different implementations between MSM8998 and
SDM845, which require different timings calculations.  Unfortunately, the
hardware designers did not choose to revise the version to account for this
delta so implement a quirk instead.

Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 7161beb23b03737fc18230a783c2718ce1a2037e..3c51df1aa2eed9f5ae36da2e62ec4b8891255afb 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -21,6 +21,9 @@
 #define dsi_phy_read(offset) msm_readl((offset))
 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
 
+/* v3.0.0 10nm implementation that requires the old timings settings */
+#define V3_0_0_10NM_OLD_TIMINGS_QUIRK  BIT(0)
+
 struct msm_dsi_phy_ops {
        int (*init) (struct msm_dsi_phy *phy);
        int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
@@ -41,6 +44,7 @@ struct msm_dsi_phy_cfg {
        bool src_pll_truthtable[DSI_MAX][DSI_MAX];
        const resource_size_t io_start[DSI_MAX];
        const int num_dsi_phy;
+       const int quirks;
 };
 
 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index b1e7dbc69fa66891abd8a591ec6235d6080623c1..eb28937f4b348e617ffd668780caa1c804bf5f53 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -42,6 +42,9 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
        u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
        void __iomem *lane_base = phy->lane_base;
 
+       if (phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)
+               tx_dctrl[3] = 0x02;
+
        /* Strength ctrl settings */
        for (i = 0; i < 5; i++) {
                dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i),
@@ -74,9 +77,11 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
                              tx_dctrl[i]);
        }
 
-       /* Toggle BIT 0 to release freeze I/0 */
-       dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
-       dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
+       if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) {
+               /* Toggle BIT 0 to release freeze I/0 */
+               dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
+               dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
+       }
 }
 
 static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
@@ -238,4 +243,5 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
        },
        .io_start = { 0xc994400, 0xc996400 },
        .num_dsi_phy = 2,
+       .quirks = V3_0_0_10NM_OLD_TIMINGS_QUIRK,
 };