clk: sunxi: Implement A10 EMAC clocks
authorJagan Teki <jagan@amarulasolutions.com>
Wed, 27 Feb 2019 18:56:49 +0000 (00:26 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Sat, 9 Mar 2019 07:46:35 +0000 (13:16 +0530)
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.

Which would eventually used in sunxi_emac.c driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/clk/sunxi/clk_a10.c
drivers/clk/sunxi/clk_a10s.c

index b8b57e2b3127b2dbfbb2475d72f47f671a3f0732..15ffe5ecb358b3028c4ee33729add821581cbbda 100644 (file)
@@ -22,6 +22,7 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
        [CLK_AHB_MMC3]          = GATE(0x060, BIT(11)),
+       [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
index c6fcede82290866fe309f80812f5d98362180141..33d41d47b0f2c299c8cabe9bc805b42435716f80 100644 (file)
@@ -19,6 +19,7 @@ static struct ccu_clk_gate a10s_gates[] = {
        [CLK_AHB_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),