drm/amdgpu: add amdgpu_mmhub_funcs definition
authorTao Zhou <tao.zhou1@amd.com>
Tue, 6 Aug 2019 12:15:55 +0000 (20:15 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 12 Aug 2019 17:47:48 +0000 (12:47 -0500)
add amdgpu_mmhub_funcs definition and initialize it,
prepare for mmhub ras enablement

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h

index f85e7174babbf1e18feccae09f0035cec7f3cfa0..63df32afe22aa0e5e35138dfaa42853b1d3b8f8e 100644 (file)
@@ -87,6 +87,7 @@
 #include "amdgpu_discovery.h"
 #include "amdgpu_mes.h"
 #include "amdgpu_umc.h"
+#include "amdgpu_mmhub.h"
 
 #define MAX_GPU_INSTANCE               16
 
@@ -976,6 +977,7 @@ struct amdgpu_device {
 
        const struct amdgpu_nbio_funcs  *nbio_funcs;
        const struct amdgpu_df_funcs    *df_funcs;
+       const struct amdgpu_mmhub_funcs *mmhub_funcs;
 
        /* delayed work_func for deferring clockgating during resume */
        struct delayed_work     delayed_init_work;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
new file mode 100644 (file)
index 0000000..2d75ecf
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __AMDGPU_MMHUB_H__
+#define __AMDGPU_MMHUB_H__
+
+struct amdgpu_mmhub_funcs {
+       void (*ras_init)(struct amdgpu_device *adev);
+       void (*query_ras_error_count)(struct amdgpu_device *adev,
+                                       void *ras_error_status);
+};
+
+#endif
+
index 0c77b9f244bbd4ec0177fe39f5d4f4ed61fcba88..7ca75d21916180f3fa9dba07503f84c10d43b36b 100644 (file)
@@ -656,6 +656,17 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
        }
 }
 
+static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
+{
+       switch (adev->asic_type) {
+       case CHIP_VEGA20:
+               adev->mmhub_funcs = &mmhub_v1_0_funcs;
+               break;
+       default:
+               break;
+       }
+}
+
 static int gmc_v9_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -663,6 +674,7 @@ static int gmc_v9_0_early_init(void *handle)
        gmc_v9_0_set_gmc_funcs(adev);
        gmc_v9_0_set_irq_funcs(adev);
        gmc_v9_0_set_umc_funcs(adev);
+       gmc_v9_0_set_mmhub_funcs(adev);
 
        adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
        adev->gmc.shared_aperture_end =
index 292f3b1cddf2c611c9989f4a17c78e42c4b0119f..fa961e0b6f2f3049f63590469bad894b38bbdd9e 100644 (file)
@@ -584,3 +584,12 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
        if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
                *flags |= AMD_CG_SUPPORT_MC_LS;
 }
+
+static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+                                          void *ras_error_status)
+{
+}
+
+const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
+       .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
+};
index 0de0fdf98c00d9c6144536620afec44dc5e66228..c43319e8f945f92a301b28f6cffa33e03fa9cf63 100644 (file)
@@ -23,6 +23,8 @@
 #ifndef __MMHUB_V1_0_H__
 #define __MMHUB_V1_0_H__
 
+extern const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs;
+
 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev);
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);