drm/radeon: Allow setting shader registers using DMA/COPY packet3 on SI.

Mesa uses a COPY_DATA packet to copy the grid size for indirect dispatches
into COMPUTE_USER_DATA_*.

Setting those registers with a SET_SH_REG packet is allowed, not allowing
them with other packets seems like an oversight.

v2: Clarify commit message.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 1ff77cea436d390bbca823f1b918577a30cf52ce..c0083f04a84247135863a2b6df99d04facb52e92 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -94,9 +94,10 @@
  *   2.42.0 - Add VCE/VUI (Video Usability Information) support
  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
  *   2.44.0 - SET_APPEND_CNT packet3 support
+ *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
  */
 #define KMS_DRIVER_MAJOR       2
-#define KMS_DRIVER_MINOR       44
+#define KMS_DRIVER_MINOR       45
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 7afe825ee561aa4b32265e1703651384d687309d..b30e719dd56d87f1a195c443de85b8fc48a462b7 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4364,6 +4364,10 @@ static bool si_vm_reg_valid(u32 reg)
        if (reg >= 0x28000)
                return true;
 
+       /* shader regs are also fine */
+       if (reg >= 0xB000 && reg < 0xC000)
+               return true;
+
        /* check config regs */
        switch (reg) {
        case GRBM_GFX_INDEX: