ARM: exynos: Remove static mapping of SCU SFR
authorPankaj Dubey <pankaj.dubey@samsung.com>
Thu, 10 May 2018 11:02:54 +0000 (13:02 +0200)
committerKrzysztof Kozlowski <krzk@kernel.org>
Sun, 13 May 2018 12:06:55 +0000 (14:06 +0200)
Lets remove static mapping of SCU SFR mainly used in CORTEX-A9 SoC based
boards. Instead use mapping from device tree node of SCU.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
[mszyprow: rebased, added fallback to scu_a9_get_base() when no SCU DT
 node is available, removed compatibility break warning, fixed non-SMP
 build, keep SCU base mapping to avoid issues with calls from CPUidle]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm/mach-exynos/common.h
arch/arm/mach-exynos/exynos.c
arch/arm/mach-exynos/include/mach/map.h
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-exynos/pm.c
arch/arm/mach-exynos/suspend.c
arch/arm/plat-samsung/include/plat/map-s5p.h

index f332c654784b0297cb66120d59b0d615163a6df0..70253f71e59ee77219e5d5f9735642100b407e5a 100644 (file)
@@ -141,6 +141,11 @@ extern void exynos_cpu_restore_register(void);
 extern void exynos_pm_central_suspend(void);
 extern int exynos_pm_central_resume(void);
 extern void exynos_enter_aftr(void);
+#ifdef CONFIG_SMP
+extern void exynos_scu_enable(void);
+#else
+static inline void exynos_scu_enable(void) { }
+#endif
 
 extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
 
index 460ae13b3145bffc3df463bd921b344d635a1c25..f4b6c93a7fd07fdc289d486e09c2f331ecfb5d21 100644 (file)
 
 #include "common.h"
 
-static struct map_desc exynos4_iodesc[] __initdata = {
-       {
-               .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
-               .length         = SZ_8K,
-               .type           = MT_DEVICE,
-       },
-};
-
 static struct platform_device exynos_cpuidle = {
        .name              = "exynos_cpuidle",
 #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@@ -85,17 +76,6 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
        return 1;
 }
 
-/*
- * exynos_map_io
- *
- * register the standard cpu IO areas
- */
-static void __init exynos_map_io(void)
-{
-       if (soc_is_exynos4())
-               iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-}
-
 static void __init exynos_init_io(void)
 {
        debug_ll_io_init();
@@ -104,8 +84,6 @@ static void __init exynos_init_io(void)
 
        /* detect cpu id and rev. */
        s5p_init_cpu(S5P_VA_CHIPID);
-
-       exynos_map_io();
 }
 
 /*
index 37a5ea5e2602a3c7ac81fc18276bb5e6c2b48229..22ebe36546330c25a85112ce867e047ad28595cc 100644 (file)
@@ -15,6 +15,4 @@
 
 #define EXYNOS_PA_CHIPID               0x10000000
 
-#define EXYNOS4_PA_COREPERI            0x10500000
-
 #endif /* __ASM_ARCH_MAP_H */
index 5156fe70e030579cf2b707fd755f70133a63926d..6a1e682371b32c400041fb2aa0db1698a19a63d3 100644 (file)
@@ -163,6 +163,26 @@ int exynos_cluster_power_state(int cluster)
                S5P_CORE_LOCAL_PWR_EN);
 }
 
+/**
+ * exynos_scu_enable : enables SCU for Cortex-A9 based system
+ */
+void exynos_scu_enable(void)
+{
+       struct device_node *np;
+       static void __iomem *scu_base;
+
+       if (!scu_base) {
+               np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+               if (np) {
+                       scu_base = of_iomap(np, 0);
+                       of_node_put(np);
+               } else {
+                       scu_base = ioremap(scu_a9_get_base(), SZ_4K);
+               }
+       }
+       scu_enable(scu_base);
+}
+
 static void __iomem *cpu_boot_reg_base(void)
 {
        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
@@ -219,11 +239,6 @@ static void write_pen_release(int val)
        sync_cache_w(&pen_release);
 }
 
-static void __iomem *scu_base_addr(void)
-{
-       return (void __iomem *)(S5P_VA_SCU);
-}
-
 static DEFINE_SPINLOCK(boot_lock);
 
 static void exynos_secondary_init(unsigned int cpu)
@@ -389,7 +404,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
        exynos_set_delayed_reset_assertion(true);
 
        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-               scu_enable(scu_base_addr());
+               exynos_scu_enable();
 
        /*
         * Write the address of secondary startup into the
index a822c507371545bc19b0a7e78adc7b7d10c196cc..48e7fb38613ebcd079bfdea7d45e27bc2501b812 100644 (file)
@@ -22,8 +22,6 @@
 #include <asm/suspend.h>
 #include <asm/cacheflush.h>
 
-#include <mach/map.h>
-
 #include "common.h"
 
 static inline void __iomem *exynos_boot_vector_addr(void)
@@ -172,7 +170,7 @@ void exynos_enter_aftr(void)
        cpu_suspend(0, exynos_aftr_finisher);
 
        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
-               scu_enable(S5P_VA_SCU);
+               exynos_scu_enable();
                if (call_firmware_op(resume) == -ENOSYS)
                        exynos_cpu_restore_register();
        }
index c2ed997fedefacc2052e950664ffa272d71cf334..d3db306a5a709a82dad9852ace9b83deca2fb1e9 100644 (file)
@@ -30,8 +30,6 @@
 #include <asm/smp_scu.h>
 #include <asm/suspend.h>
 
-#include <mach/map.h>
-
 #include <plat/pm-common.h>
 
 #include "common.h"
@@ -401,7 +399,7 @@ static void exynos_pm_resume(void)
                goto early_wakeup;
 
        if (cpuid == ARM_CPU_PART_CORTEX_A9)
-               scu_enable(S5P_VA_SCU);
+               exynos_scu_enable();
 
        if (call_firmware_op(resume) == -ENOSYS
            && cpuid == ARM_CPU_PART_CORTEX_A9)
index f5769e93544a95805e5f87bfc727c3407ed244c1..d69a0ca09fb5b84eda2fe27363319cbd53cd777d 100644 (file)
 
 #define S5P_VA_CHIPID          S3C_ADDR(0x02000000)
 
-#define S5P_VA_COREPERI_BASE   S3C_ADDR(0x02800000)
-#define S5P_VA_COREPERI(x)     (S5P_VA_COREPERI_BASE + (x))
-#define S5P_VA_SCU             S5P_VA_COREPERI(0x0)
-
 #define VA_VIC(x)              (S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0                        VA_VIC(0)
 #define VA_VIC1                        VA_VIC(1)