mvebu: cp110: fix spelling in register definition

Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).

Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 925abb5e51a13d6d8abad7668a0b577456970168..6afa2c22787838e9f7482d56e4997af4b2817c54 100644 (file)
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -217,9 +217,9 @@
 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET    0
 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK      \
                        (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET    3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK      \
-                       (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET    3
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK      \
+                       (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET    6
 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK      \
                        (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
@@ -251,9 +251,9 @@
 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET    0
 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK      \
                        (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET    3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK      \
-                       (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET    3
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK      \
+                       (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET    6
 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK      \
                        (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)

diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 326d5a85ddefdabdc1368555ba216e0effe16606..19bd182fa927358b8f20f1ad2c0318bda17fee7a 100644 (file)
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -481,8 +481,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
        /* G1 settings */
        mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
        data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-       mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-       data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+       mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+       data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
        mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
        data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
        mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
@@ -506,8 +506,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
        /* G2 settings */
        mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
        data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
-       mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
-       data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+       mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
+       data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
        mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
        data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
        mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
@@ -1000,13 +1000,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
        if (speed == COMPHY_SPEED_5_15625G) {
                mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
                data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-               data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+               data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
        } else {
                mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
                data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-               data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+               mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+               data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
                mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
                data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
                mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
@@ -1504,8 +1504,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base,
        /* Genration 2 setting 1*/
        mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
        data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
-       mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
-       data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+       mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
+       data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
        mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
        data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
        reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
@@ -1741,8 +1741,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base,
        /* 0xE-G1_Setting_1 */
        mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
        data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-       mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-       data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+       mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+       data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
        mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
        data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
        reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);