drm/amd/display: Add timing generator count to resource pool.

Use tg count in resource pool for further reference.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 442dd2d93618d57eeff5c21ae576750f86c50416..3bdbed80f7f8a98d1511f4c97a07ba400c4df061 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -849,6 +849,7 @@ static bool construct(
        *************************************************/
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap.num_timing_generator;
+       pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 0f84306dd28e8a7426d8893782f0c876a40e7458..c4e877ac95d30a4792013057389c1adaa3f6636a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1152,7 +1152,7 @@ static bool construct(
 
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.underlay_pipe_index = pool->base.pipe_count;
-
+       pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 150;
        dc->caps.i2c_speed_in_khz = 100;
        dc->caps.max_cursor_size = 128;

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 98d9cd0109e1f3cf5dbfa7b9111353c163aa4ad4..c0757dd6c03c999fb3e4334a4b7becc18be4e887 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1100,6 +1100,7 @@ static bool construct(
         *************************************************/
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+       pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
        dc->caps.max_cursor_size = 128;

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index a8725ac11a2cd199684a558f97258c36ceb50212..4659a4bfabaa2ff3e64f7502b3940ee1ce642c98 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -831,6 +831,7 @@ static bool construct(
 
        /* TODO: Fill more data from GreenlandAsicCapability.cpp */
        pool->base.pipe_count = res_cap.num_timing_generator;
+       pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
        dc->caps.max_downscale_ratio = 200;

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 25d7eb1567aeb10bc61d23df101f6b3303fe107c..a36c14d3d9a86f586a468cad9517cb7bfa298b89 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -790,6 +790,7 @@ static bool dce80_construct(
         *************************************************/
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap.num_timing_generator;
+       pool->base.timing_generator_count = res_cap.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;
@@ -955,6 +956,7 @@ static bool dce81_construct(
         *************************************************/
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap_81.num_timing_generator;
+       pool->base.timing_generator_count = res_cap_81.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;
@@ -1120,6 +1122,7 @@ static bool dce83_construct(
         *************************************************/
        pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap_83.num_timing_generator;
+       pool->base.timing_generator_count = res_cap_83.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c6a4fa2f17c2805e5452028efcebaef3de7b4a0e..e1a8ebae371476e346f0f9f68ebf7e5bd0a5fad5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -133,7 +133,7 @@ void dcn10_log_hw_state(struct dc *dc)
                DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
                                "%xh \t %xh \t %xh \t "
                                "%d \t %d \t %d \t %xh \t",
-                               i,
+                               hubp->inst,
                                s.pixel_format,
                                s.inuse_addr_hi,
                                s.viewport_width,
@@ -155,7 +155,7 @@ void dcn10_log_hw_state(struct dc *dc)
        DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
                        "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 
-       for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+       for (i = 0; i < pool->timing_generator_count; i++) {
                struct timing_generator *tg = pool->timing_generators[i];
                struct dcn_otg_state s = {0};
 
@@ -168,7 +168,7 @@ void dcn10_log_hw_state(struct dc *dc)
                DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
                                "%d \t %d \t %d \t %d \t %d \t %d \t "
                                "%d \t %d \t %d \t %d \t %d \t ",
-                               i,
+                               tg->inst,
                                s.v_blank_start,
                                s.v_blank_end,
                                s.v_sync_a_start,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 66af05b03e0fd939cc4f124d44137df4c503c778..ed616f5e4265ce2d6d10c38291544ae14cd050ce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1445,6 +1445,7 @@ static bool construct(
 
        /* valid pipe num */
        pool->base.pipe_count = j;
+       pool->base.timing_generator_count = j;
 
        /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
         * the value may be changed

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 59d2699b17ce89122c34e8576faf93745af2c42d..5509e13e7edfa8272005663eca98cb00bffbdcfd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -153,6 +153,7 @@ struct resource_pool {
        unsigned int underlay_pipe_index;
        unsigned int stream_enc_count;
        unsigned int ref_clock_inKhz;
+       unsigned int timing_generator_count;
 
        /*
         * reserved clock source for DP