--- /dev/null
+From 3b2e7c7c83873f4c073d501c2fff80518e264240 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Jan 2016 20:24:00 +0100
+Subject: [PATCH] MIPS: ralink: Add a few missing clocks
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/11995/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ralink/mt7620.c | 3 +++
+ arch/mips/ralink/rt305x.c | 1 +
+ arch/mips/ralink/rt3883.c | 1 +
+ 3 files changed, 5 insertions(+)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -436,7 +436,10 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("10000100.timer", periph_rate);
+ ralink_clk_add("10000120.watchdog", periph_rate);
+ ralink_clk_add("10000b00.spi", sys_rate);
++ ralink_clk_add("10000b40.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", periph_rate);
++ ralink_clk_add("10000d00.uart1", periph_rate);
++ ralink_clk_add("10000e00.uart2", periph_rate);
+ ralink_clk_add("10180000.wmac", xtal_rate);
+
+ if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -201,6 +201,7 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("cpu", cpu_rate);
+ ralink_clk_add("sys", sys_rate);
+ ralink_clk_add("10000b00.spi", sys_rate);
++ ralink_clk_add("10000b40.spi", sys_rate);
+ ralink_clk_add("10000100.timer", wdt_rate);
+ ralink_clk_add("10000120.watchdog", wdt_rate);
+ ralink_clk_add("10000500.uart", uart_rate);
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("10000120.watchdog", sys_rate);
+ ralink_clk_add("10000500.uart", 40000000);
+ ralink_clk_add("10000b00.spi", sys_rate);
++ ralink_clk_add("10000b40.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", 40000000);
+ ralink_clk_add("10100000.ethernet", sys_rate);
+ ralink_clk_add("10180000.wmac", 40000000);
+++ /dev/null
-From 39ce22c870f4503bed5e451acfcab21eba3b6239 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:49:07 +0100
-Subject: [PATCH 10/53] arch: mips: ralink: add spi1 clocks
-
-based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 1 +
- arch/mips/ralink/rt305x.c | 1 +
- arch/mips/ralink/rt3883.c | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -436,6 +436,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000100.timer", periph_rate);
- ralink_clk_add("10000120.watchdog", periph_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
-+ ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -201,6 +201,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("sys", sys_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
-+ ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000100.timer", wdt_rate);
- ralink_clk_add("10000120.watchdog", wdt_rate);
- ralink_clk_add("10000500.uart", uart_rate);
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000120.watchdog", sys_rate);
- ralink_clk_add("10000500.uart", 40000000);
- ralink_clk_add("10000b00.spi", sys_rate);
-+ ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", 40000000);
- ralink_clk_add("10100000.ethernet", sys_rate);
- ralink_clk_add("10180000.wmac", 40000000);
--- /dev/null
+From 3bca798b859c75063b3b4e65f6b019c7a4bd53ef Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Jan 2016 20:23:59 +0100
+Subject: [PATCH] MIPS: ralink: Fix vendor string for mt7620
+
+Ralink was acquired by Mediatek. Represent this in the cpuinfo. It
+apparently confused people.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/11994/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ralink/mt7620.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -555,7 +555,7 @@ void prom_soc_init(struct ralink_soc_inf
+ }
+
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+- "Ralink %s ver:%u eco:%u",
++ "MediaTek %s ver:%u eco:%u",
+ name,
+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
+ (rev & CHIP_REV_ECO_MASK));
+++ /dev/null
-From 2e5d90398aacde3e46dfd87e6f716b00a0ffcd83 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:30:11 +0100
-Subject: [PATCH 22/53] arch: mips: ralink: proper vendor id srtring
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -553,7 +553,7 @@ void prom_soc_init(struct ralink_soc_inf
- }
-
- snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
-- "Ralink %s ver:%u eco:%u",
-+ "MediaTek %s ver:%u eco:%u",
- name,
- (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
- (rev & CHIP_REV_ECO_MASK));
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
-@@ -1354,6 +1354,13 @@ config RALINK_WDT
+@@ -1345,6 +1345,13 @@ config RALINK_WDT
help
Hardware driver for the Ralink SoC Watchdog Timer.
static int macronix_quad_enable(struct spi_nor *nor)
{
int ret, val;
-@@ -1185,10 +1245,12 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1186,10 +1246,12 @@ int spi_nor_scan(struct spi_nor *nor, co
}
/* sst nor chips use AAI word program */
if (info->flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
-@@ -1216,11 +1278,20 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1217,11 +1279,20 @@ int spi_nor_scan(struct spi_nor *nor, co
mtd->writebufsize = nor->page_size;
if (np) {
--- /dev/null
+From e906a5f67e5a3337d696ec848e9c28fc68b39aa3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Jan 2016 20:23:56 +0100
+Subject: [PATCH] MIPS: ralink: MT7688 pinmux fixes
+
+A few fixes to the pinmux data, 2 new muxes and a minor whitespace
+cleanup.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/11991/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ralink/mt7620.c | 80 +++++++++++++++++++++++++++++------------------
+ 1 file changed, 50 insertions(+), 30 deletions(-)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -107,31 +107,31 @@ static struct rt2880_pmx_group mt7620a_p
+ };
+
+ static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
+- FUNC("sdcx", 3, 19, 1),
++ FUNC("sdxc d6", 3, 19, 1),
+ FUNC("utif", 2, 19, 1),
+ FUNC("gpio", 1, 19, 1),
+- FUNC("pwm", 0, 19, 1),
++ FUNC("pwm1", 0, 19, 1),
+ };
+
+ static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
+- FUNC("sdcx", 3, 18, 1),
++ FUNC("sdxc d7", 3, 18, 1),
+ FUNC("utif", 2, 18, 1),
+ FUNC("gpio", 1, 18, 1),
+- FUNC("pwm", 0, 18, 1),
++ FUNC("pwm0", 0, 18, 1),
+ };
+
+ static struct rt2880_pmx_func uart2_grp_mt7628[] = {
+- FUNC("sdcx", 3, 20, 2),
++ FUNC("sdxc d5 d4", 3, 20, 2),
+ FUNC("pwm", 2, 20, 2),
+ FUNC("gpio", 1, 20, 2),
+- FUNC("uart", 0, 20, 2),
++ FUNC("uart2", 0, 20, 2),
+ };
+
+ static struct rt2880_pmx_func uart1_grp_mt7628[] = {
+- FUNC("sdcx", 3, 45, 2),
++ FUNC("sw_r", 3, 45, 2),
+ FUNC("pwm", 2, 45, 2),
+ FUNC("gpio", 1, 45, 2),
+- FUNC("uart", 0, 45, 2),
++ FUNC("uart1", 0, 45, 2),
+ };
+
+ static struct rt2880_pmx_func i2c_grp_mt7628[] = {
+@@ -143,21 +143,21 @@ static struct rt2880_pmx_func i2c_grp_mt
+
+ static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
+ static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
+-static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
++static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
+ static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
+
+ static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
+ FUNC("jtag", 3, 22, 8),
+ FUNC("utif", 2, 22, 8),
+ FUNC("gpio", 1, 22, 8),
+- FUNC("sdcx", 0, 22, 8),
++ FUNC("sdxc", 0, 22, 8),
+ };
+
+ static struct rt2880_pmx_func uart0_grp_mt7628[] = {
+ FUNC("-", 3, 12, 2),
+ FUNC("-", 2, 12, 2),
+ FUNC("gpio", 1, 12, 2),
+- FUNC("uart", 0, 12, 2),
++ FUNC("uart0", 0, 12, 2),
+ };
+
+ static struct rt2880_pmx_func i2s_grp_mt7628[] = {
+@@ -171,7 +171,7 @@ static struct rt2880_pmx_func spi_cs1_gr
+ FUNC("-", 3, 6, 1),
+ FUNC("refclk", 2, 6, 1),
+ FUNC("gpio", 1, 6, 1),
+- FUNC("spi", 0, 6, 1),
++ FUNC("spi cs1", 0, 6, 1),
+ };
+
+ static struct rt2880_pmx_func spis_grp_mt7628[] = {
+@@ -188,28 +188,44 @@ static struct rt2880_pmx_func gpio_grp_m
+ FUNC("gpio", 0, 11, 1),
+ };
+
+-#define MT7628_GPIO_MODE_MASK 0x3
+-
+-#define MT7628_GPIO_MODE_PWM1 30
+-#define MT7628_GPIO_MODE_PWM0 28
+-#define MT7628_GPIO_MODE_UART2 26
+-#define MT7628_GPIO_MODE_UART1 24
+-#define MT7628_GPIO_MODE_I2C 20
+-#define MT7628_GPIO_MODE_REFCLK 18
+-#define MT7628_GPIO_MODE_PERST 16
+-#define MT7628_GPIO_MODE_WDT 14
+-#define MT7628_GPIO_MODE_SPI 12
+-#define MT7628_GPIO_MODE_SDMODE 10
+-#define MT7628_GPIO_MODE_UART0 8
+-#define MT7628_GPIO_MODE_I2S 6
+-#define MT7628_GPIO_MODE_CS1 4
+-#define MT7628_GPIO_MODE_SPIS 2
+-#define MT7628_GPIO_MODE_GPIO 0
++static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
++ FUNC("rsvd", 3, 35, 1),
++ FUNC("rsvd", 2, 35, 1),
++ FUNC("gpio", 1, 35, 1),
++ FUNC("wled_kn", 0, 35, 1),
++};
++
++static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
++ FUNC("rsvd", 3, 35, 1),
++ FUNC("rsvd", 2, 35, 1),
++ FUNC("gpio", 1, 35, 1),
++ FUNC("wled_an", 0, 35, 1),
++};
++
++#define MT7628_GPIO_MODE_MASK 0x3
++
++#define MT7628_GPIO_MODE_WLED_KN 48
++#define MT7628_GPIO_MODE_WLED_AN 32
++#define MT7628_GPIO_MODE_PWM1 30
++#define MT7628_GPIO_MODE_PWM0 28
++#define MT7628_GPIO_MODE_UART2 26
++#define MT7628_GPIO_MODE_UART1 24
++#define MT7628_GPIO_MODE_I2C 20
++#define MT7628_GPIO_MODE_REFCLK 18
++#define MT7628_GPIO_MODE_PERST 16
++#define MT7628_GPIO_MODE_WDT 14
++#define MT7628_GPIO_MODE_SPI 12
++#define MT7628_GPIO_MODE_SDMODE 10
++#define MT7628_GPIO_MODE_UART0 8
++#define MT7628_GPIO_MODE_I2S 6
++#define MT7628_GPIO_MODE_CS1 4
++#define MT7628_GPIO_MODE_SPIS 2
++#define MT7628_GPIO_MODE_GPIO 0
+
+ static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
+ GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
+ 1, MT7628_GPIO_MODE_PWM1),
+- GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
++ GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
+ 1, MT7628_GPIO_MODE_PWM0),
+ GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
+ 1, MT7628_GPIO_MODE_UART2),
+@@ -233,6 +249,10 @@ static struct rt2880_pmx_group mt7628an_
+ 1, MT7628_GPIO_MODE_SPIS),
+ GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
+ 1, MT7628_GPIO_MODE_GPIO),
++ GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
++ 1, MT7628_GPIO_MODE_WLED_AN),
++ GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
++ 1, MT7628_GPIO_MODE_WLED_KN),
+ { 0 }
+ };
+
+++ /dev/null
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -107,31 +107,31 @@ static struct rt2880_pmx_group mt7620a_p
- };
-
- static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
-- FUNC("sdcx", 3, 19, 1),
-+ FUNC("sdxc", 3, 19, 1),
- FUNC("utif", 2, 19, 1),
- FUNC("gpio", 1, 19, 1),
- FUNC("pwm", 0, 19, 1),
- };
-
- static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
-- FUNC("sdcx", 3, 18, 1),
-+ FUNC("sdxc", 3, 18, 1),
- FUNC("utif", 2, 18, 1),
- FUNC("gpio", 1, 18, 1),
- FUNC("pwm", 0, 18, 1),
- };
-
- static struct rt2880_pmx_func uart2_grp_mt7628[] = {
-- FUNC("sdcx", 3, 20, 2),
-+ FUNC("sdxc", 3, 20, 2),
- FUNC("pwm", 2, 20, 2),
- FUNC("gpio", 1, 20, 2),
-- FUNC("uart", 0, 20, 2),
-+ FUNC("uart2", 0, 20, 2),
- };
-
- static struct rt2880_pmx_func uart1_grp_mt7628[] = {
- FUNC("sdcx", 3, 45, 2),
- FUNC("pwm", 2, 45, 2),
- FUNC("gpio", 1, 45, 2),
-- FUNC("uart", 0, 45, 2),
-+ FUNC("uart1", 0, 45, 2),
- };
-
- static struct rt2880_pmx_func i2c_grp_mt7628[] = {
-@@ -143,21 +143,21 @@ static struct rt2880_pmx_func i2c_grp_mt
-
- static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
- static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
--static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
-+static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
- static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
-
- static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
- FUNC("jtag", 3, 22, 8),
- FUNC("utif", 2, 22, 8),
- FUNC("gpio", 1, 22, 8),
-- FUNC("sdcx", 0, 22, 8),
-+ FUNC("sdxc", 0, 22, 8),
- };
-
- static struct rt2880_pmx_func uart0_grp_mt7628[] = {
- FUNC("-", 3, 12, 2),
- FUNC("-", 2, 12, 2),
- FUNC("gpio", 1, 12, 2),
-- FUNC("uart", 0, 12, 2),
-+ FUNC("uart0", 0, 12, 2),
- };
-
- static struct rt2880_pmx_func i2s_grp_mt7628[] = {
-@@ -438,6 +438,8 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
-+ ralink_clk_add("10000d00.uart1", periph_rate);
-+ ralink_clk_add("10000e00.uart2", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-
- if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
-@@ -442,7 +442,7 @@ void __init ralink_clk_init(void)
+@@ -462,7 +462,7 @@ void __init ralink_clk_init(void)
ralink_clk_add("10000e00.uart2", periph_rate);
ralink_clk_add("10180000.wmac", xtal_rate);
--- /dev/null
+From 0af3a40f09a2a85089037a0b5b51471fa48b229e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Jan 2016 20:23:58 +0100
+Subject: [PATCH] MIPS: ralink: Fix invalid assignment of SoC type
+
+Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") introduced
+broken code. We obviously need to assign the value.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/11993/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ralink/rt288x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -119,5 +119,5 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
+
+ rt2880_pinmux_data = rt2880_pinmux_data_act;
+- ralink_soc == RT2880_SOC;
++ ralink_soc = RT2880_SOC;
+ }
projects / openwrt / staging / wigyori.git / commitdiff