powerpc/setup_64: fix -Wempty-body warnings

At the beginning of setup_64.c, it has,

  #ifdef DEBUG
  #define DBG(fmt...) udbg_printf(fmt)
  #else
  #define DBG(fmt...)
  #endif

where DBG() could be compiled away, and generate warnings,

  arch/powerpc/kernel/setup_64.c: In function 'initialize_cache_info':
  arch/powerpc/kernel/setup_64.c:579:49: warning: suggest braces around
  empty body in an 'if' statement [-Wempty-body]
      DBG("Argh, can't find dcache properties !\n");
                                                 ^
  arch/powerpc/kernel/setup_64.c:582:49: warning: suggest braces around
  empty body in an 'if' statement [-Wempty-body]
      DBG("Argh, can't find icache properties !\n");

Fix it by using the suggestions from Michael:

  "Neither of those sites should use DBG(), that's not really early
  boot code, they should just use pr_warn().

  And the other uses of DBG() in initialize_cache_info() should just
  be removed.

  In smp_release_cpus() the entry/exit DBG's should just be removed,
  and the spinning_secondaries line should just be pr_debug().

  That would just leave the two calls in early_setup(). If we taught
  udbg_printf() to return early when udbg_putc is NULL, then we could
  just call udbg_printf() unconditionally and get rid of the DBG macro
  entirely."

Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Qian Cai <cai@lca.pw>
[mpe: Split udbg change out into previous patch]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1563215552-8166-1-git-send-email-cai@lca.pw

diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 44b4c432a27365cc2a60fbb58297577936b9985c..d2af4c228970e66019ab98dab1af2c6eefd24af8 100644 (file)
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -68,12 +68,6 @@
 
 #include "setup.h"
 
-#ifdef DEBUG
-#define DBG(fmt...) udbg_printf(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
 int spinning_secondaries;
 u64 ppc64_pft_size;
 
@@ -305,7 +299,7 @@ void __init early_setup(unsigned long dt_ptr)
        /* Enable early debugging if any specified (see udbg.h) */
        udbg_early_init();
 
-       DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
+       udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
 
        /*
         * Do early initialization using the flattened device
@@ -362,11 +356,11 @@ void __init early_setup(unsigned long dt_ptr)
         */
        this_cpu_enable_ftrace();
 
-       DBG(" <- early_setup()\n");
+       udbg_printf(" <- %s()\n", __func__);
 
 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
        /*
-        * This needs to be done *last* (after the above DBG() even)
+        * This needs to be done *last* (after the above udbg_printf() even)
         *
         * Right after we return from this function, we turn on the MMU
         * which means the real-mode access trick that btext does will
@@ -436,8 +430,6 @@ void smp_release_cpus(void)
        if (!use_spinloop())
                return;
 
-       DBG(" -> smp_release_cpus()\n");
-
        /* All secondary cpus are spinning on a common spinloop, release them
         * all now so they can start to spin on their individual paca
         * spinloops. For non SMP kernels, the secondary cpus never get out
@@ -456,9 +448,7 @@ void smp_release_cpus(void)
                        break;
                udelay(1);
        }
-       DBG("spinning_secondaries = %d\n", spinning_secondaries);
-
-       DBG(" <- smp_release_cpus()\n");
+       pr_debug("spinning_secondaries = %d\n", spinning_secondaries);
 }
 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
 
@@ -551,8 +541,6 @@ void __init initialize_cache_info(void)
        struct device_node *cpu = NULL, *l2, *l3 = NULL;
        u32 pvr;
 
-       DBG(" -> initialize_cache_info()\n");
-
        /*
         * All shipping POWER8 machines have a firmware bug that
         * puts incorrect information in the device-tree. This will
@@ -576,10 +564,10 @@ void __init initialize_cache_info(void)
         */
        if (cpu) {
                if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
-                       DBG("Argh, can't find dcache properties !\n");
+                       pr_warn("Argh, can't find dcache properties !\n");
 
                if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
-                       DBG("Argh, can't find icache properties !\n");
+                       pr_warn("Argh, can't find icache properties !\n");
 
                /*
                 * Try to find the L2 and L3 if any. Assume they are
@@ -604,8 +592,6 @@ void __init initialize_cache_info(void)
 
        cur_cpu_spec->dcache_bsize = dcache_bsize;
        cur_cpu_spec->icache_bsize = icache_bsize;
-
-       DBG(" <- initialize_cache_info()\n");
 }
 
 /*