hikey: Add BL32 (OP-TEE) support

Signed-off-by: Victor Chong <victor.chong@linaro.org>

diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index d513ae3308a303c96226d90d98f563b48dc71116..125941f883693be72cd87d61cf93cfd1ed4797e0 100644 (file)
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -14,6 +14,9 @@ Code Locations
 -  ARM Trusted Firmware:
    `link <https://github.com/ARM-software/arm-trusted-firmware>`__
 
+-  OP-TEE
+   `link <https://github.com/OP-TEE/optee_os>`__
+
 -  edk2:
    `link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
 
@@ -70,7 +73,7 @@ Build Procedure
        FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
        cd ${EDK2_DIR}
        # Build UEFI & ARM Trust Firmware
-       ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware hikey
+       ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey
        # Generate l-loader.bin
        cd ${BUILD_PATH}/l-loader
        ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin

diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c
index d8a68cf622e8957ac8933a9396f1f1d606febbfb..20a95bf70c77316e116cff58a606631e7135f536 100644 (file)
--- a/plat/hisilicon/hikey/aarch64/hikey_common.c
+++ b/plat/hisilicon/hikey/aarch64/hikey_common.c
@@ -24,6 +24,10 @@
                                        DEVICE_SIZE,                    \
                                        MT_DEVICE | MT_RW | MT_SECURE)
 
+#define MAP_TSP_MEM    MAP_REGION_FLAT(TSP_SEC_MEM_BASE,               \
+                                       TSP_SEC_MEM_SIZE,               \
+                                       MT_MEMORY | MT_RW | MT_SECURE)
+
 #define MAP_ROM_PARAM  MAP_REGION_FLAT(XG2RAM0_BASE,                   \
                                        BL1_XG2RAM0_OFFSET,             \
                                        MT_DEVICE | MT_RO | MT_SECURE)
@@ -59,6 +63,7 @@ static const mmap_region_t hikey_mmap[] = {
 static const mmap_region_t hikey_mmap[] = {
        MAP_DDR,
        MAP_DEVICE,
+       MAP_TSP_MEM,
        {0}
 };
 #endif
@@ -67,6 +72,15 @@ static const mmap_region_t hikey_mmap[] = {
 static const mmap_region_t hikey_mmap[] = {
        MAP_DEVICE,
        MAP_SRAM,
+       MAP_TSP_MEM,
+       {0}
+};
+#endif
+
+#if IMAGE_BL32
+static const mmap_region_t hikey_mmap[] = {
+       MAP_DEVICE,
+       MAP_DDR,
        {0}
 };
 #endif

diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index 9e9909b9de4d2ed94e56ff62b41030f6aec3c085..13dc6c9b839d03abbe1c719e50118abb57336896 100644 (file)
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -144,6 +144,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image,
                                       DISABLE_ALL_EXCEPTIONS);
 }
 
+/*******************************************************************************
+ * Before calling this function BL32 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL32 and set SPSR and security state.
+ * On Hikey we only set the security state of the entrypoint
+ ******************************************************************************/
+#ifdef BL32_BASE
+void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
+                                       entry_point_info_t *bl32_ep_info)
+{
+       SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
+       /*
+        * The Secure Payload Dispatcher service is responsible for
+        * setting the SPSR prior to entry into the BL32 image.
+        */
+       bl32_ep_info->spsr = 0;
+}
+
+/*******************************************************************************
+ * Populate the extents of memory available for loading BL32
+ ******************************************************************************/
+void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
+{
+       /*
+        * Populate the extents of memory available for loading BL32.
+        */
+       bl32_meminfo->total_base = BL32_BASE;
+       bl32_meminfo->free_base = BL32_BASE;
+       bl32_meminfo->total_size =
+                       (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+       bl32_meminfo->free_size =
+                       (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+}
+#endif /* BL32_BASE */
+
 void bl2_plat_set_bl33_ep_info(image_info_t *image,
                               entry_point_info_t *bl33_ep_info)
 {

diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/hikey_def.h
index 410711b38a63f2f5fd94cf94f1aaa38076b2ab24..bbad10f771dcdb79c1f9dd0ee39853fe94aa2123 100644 (file)
--- a/plat/hisilicon/hikey/hikey_def.h
+++ b/plat/hisilicon/hikey/hikey_def.h
@@ -20,6 +20,25 @@
 #define XG2RAM0_BASE                   0xF9800000
 #define XG2RAM0_SIZE                   0x00400000
 
+/* Memory location options for TSP */
+#define HIKEY_SRAM_ID          0
+#define HIKEY_DRAM_ID          1
+
+/*
+ * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
+ * regions
+ *   - Secure DDR (default is the top 16MB) used by OP-TEE
+ *   - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
+ *   - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
+ *   - Non-secure DDR (8MB) reserved for OP-TEE's future use
+ */
+#define DDR_SEC_SIZE                   0x01000000
+#define DDR_SEC_BASE                   (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE)
+
+#define DDR_SDP_SIZE                   0x00400000
+#define DDR_SDP_BASE                   (DDR_SEC_BASE - 0x400000 /* align */ - \
+                                       DDR_SDP_SIZE)
+
 #define SRAM_BASE                      0xFFF80000
 #define SRAM_SIZE                      0x00012000
 

diff --git a/plat/hisilicon/hikey/hikey_io_storage.c b/plat/hisilicon/hikey/hikey_io_storage.c
index 4ca1846fcf847c6d82760f048849246cd4849cea..c61ec2c184d7b5d29f2e3c1de3802c246607aa19 100644 (file)
--- a/plat/hisilicon/hikey/hikey_io_storage.c
+++ b/plat/hisilicon/hikey/hikey_io_storage.c
@@ -73,6 +73,10 @@ static const io_uuid_spec_t bl31_uuid_spec = {
        .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
 };
 
+static const io_uuid_spec_t bl32_uuid_spec = {
+       .uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
 static const io_uuid_spec_t bl33_uuid_spec = {
        .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
 };
@@ -102,6 +106,11 @@ static const struct plat_io_policy policies[] = {
                (uintptr_t)&bl31_uuid_spec,
                check_fip
        },
+       [BL32_IMAGE_ID] = {
+               &fip_dev_handle,
+               (uintptr_t)&bl32_uuid_spec,
+               check_fip
+       },
        [BL33_IMAGE_ID] = {
                &fip_dev_handle,
                (uintptr_t)&bl33_uuid_spec,

diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h
index 4f0aae1bfb195019a6d39c90a84224a5cbbc14de..af152322ab6ce6adc5d207cf79916cd9043df96c 100644 (file)
--- a/plat/hisilicon/hikey/include/platform_def.h
+++ b/plat/hisilicon/hikey/include/platform_def.h
@@ -97,6 +97,33 @@
 #define BL31_BASE                      BL2_LIMIT
 #define BL31_LIMIT                     0xF9898000
 
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM or SRAM.
+ */
+#define BL32_SRAM_BASE                 BL31_LIMIT
+#define BL32_SRAM_LIMIT                        (BL31_LIMIT+0x80000) /* 512K */
+
+#define BL32_DRAM_BASE                 DDR_SEC_BASE
+#define BL32_DRAM_LIMIT                        (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
+#define TSP_SEC_MEM_BASE               BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE               (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE                      BL32_DRAM_BASE
+#define BL32_LIMIT                     BL32_DRAM_LIMIT
+#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
+#define TSP_SEC_MEM_BASE               BL32_SRAM_BASE
+#define TSP_SEC_MEM_SIZE               (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
+#define BL32_BASE                      BL32_SRAM_BASE
+#define BL32_LIMIT                     BL32_SRAM_LIMIT
+#else
+#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
+#endif
+
 #define NS_BL1U_BASE                   (BL2_BASE)
 #define NS_BL1U_SIZE                   (0x00010000)
 #define NS_BL1U_LIMIT                  (NS_BL1U_BASE + NS_BL1U_SIZE)
@@ -106,10 +133,14 @@
  */
 #define ADDR_SPACE_SIZE                        (1ull << 32)
 
-#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
+#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL32
 #define MAX_XLAT_TABLES                        3
 #endif
 
+#if IMAGE_BL31
+#define MAX_XLAT_TABLES                        4
+#endif
+
 #define MAX_MMAP_REGIONS               16
 
 #define HIKEY_NS_IMAGE_OFFSET          (DDR_BASE + 0x35000000)

diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index 9543107e26a2c3da3aaebcd1f7e105f8168efe08..8da3998806c913b80c5a2740b5e7dbdfc220d942 100644 (file)
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -4,6 +4,17 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
+# or SRAM.
+HIKEY_TSP_RAM_LOCATION :=      dram
+ifeq (${HIKEY_TSP_RAM_LOCATION}, dram)
+  HIKEY_TSP_RAM_LOCATION_ID = HIKEY_DRAM_ID
+else ifeq (${HIKEY_TSP_RAM_LOCATION}, sram)
+  HIKEY_TSP_RAM_LOCATION_ID := HIKEY_SRAM_ID
+else
+  $(error "Currently unsupported HIKEY_TSP_RAM_LOCATION value")
+endif
+
 CONSOLE_BASE                   :=      PL011_UART3_BASE
 CRASH_CONSOLE_BASE             :=      PL011_UART3_BASE
 PLAT_PARTITION_MAX_ENTRIES     :=      12
@@ -12,6 +23,7 @@ COLD_BOOT_SINGLE_CPU          :=      1
 PROGRAMMABLE_RESET_ADDRESS     :=      1
 
 # Process flags
+$(eval $(call add_define,HIKEY_TSP_RAM_LOCATION_ID))
 $(eval $(call add_define,CONSOLE_BASE))
 $(eval $(call add_define,CRASH_CONSOLE_BASE))
 $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))