Backport krait clock modernization patch.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- /dev/null
+From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 12 Apr 2022 16:48:39 +0200
+Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table
+ API
+
+Introduce (devm_)hw_register_mux_parent_data_table new API. We have
+basic support for clk_register_mux using parent_data but we lack any API
+to provide a custom parent_map. Add these 2 new API to correctly handle
+these special configuration instead of using the generic
+__(devm_)clk_hw_register_mux API.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ include/linux/clk-provider.h | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/include/linux/clk-provider.h
++++ b/include/linux/clk-provider.h
+@@ -932,12 +932,26 @@ struct clk *clk_register_mux_table(struc
+ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
+ (parent_data), (flags), (reg), (shift), \
+ BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
++#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
++ num_parents, flags, reg, shift, \
++ width, clk_mux_flags, table, \
++ lock) \
++ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
++ (parent_data), (flags), (reg), (shift), \
++ BIT((width)) - 1, (clk_mux_flags), table, (lock))
+ #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
+ shift, width, clk_mux_flags, lock) \
+ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
+ (parent_names), NULL, NULL, (flags), (reg), \
+ (shift), BIT((width)) - 1, (clk_mux_flags), \
+ NULL, (lock))
++#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
++ num_parents, flags, reg, shift, \
++ width, clk_mux_flags, table, \
++ lock) \
++ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
++ NULL, (parent_data), (flags), (reg), (shift), \
++ BIT((width)) - 1, (clk_mux_flags), table, (lock))
+
+ int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
+ unsigned int val);
--- /dev/null
+From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 17 Feb 2022 22:43:34 +0100
+Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API
+
+Convert the driver to parent data API. From the Documentation pll8_vote
+and pxo should be declared in the DTS so fw_name can be used instead of
+parent_names. Name is still used to save regression on old definition.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/kpss-xcc.c | 26 +++++++++-----------------
+ 1 file changed, 9 insertions(+), 17 deletions(-)
+
+--- a/drivers/clk/qcom/kpss-xcc.c
++++ b/drivers/clk/qcom/kpss-xcc.c
+@@ -12,9 +12,9 @@
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+
+-static const char *aux_parents[] = {
+- "pll8_vote",
+- "pxo",
++static const struct clk_parent_data aux_parents[] = {
++ { .name = "pll8_vote", .fw_name = "pll8_vote" },
++ { .name = "pxo", .fw_name = "pxo" },
+ };
+
+ static unsigned int aux_parent_map[] = {
+@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
+ static int kpss_xcc_driver_probe(struct platform_device *pdev)
+ {
+ const struct of_device_id *id;
+- struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
++ struct clk_hw *hw;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, &pdev->dev);
+@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct
+ base += 0x28;
+ }
+
+- clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
+- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+- 0, aux_parent_map, NULL);
++ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
++ ARRAY_SIZE(aux_parents), 0,
++ base, 0, 0x3,
++ 0, aux_parent_map, NULL);
+
+- platform_set_drvdata(pdev, clk);
+-
+- return PTR_ERR_OR_ZERO(clk);
+-}
+-
+-static int kpss_xcc_driver_remove(struct platform_device *pdev)
+-{
+- clk_unregister_mux(platform_get_drvdata(pdev));
+- return 0;
++ return PTR_ERR_OR_ZERO(hw);
+ }
+
+ static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+- .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
--- /dev/null
+From 3a0cf0a2b99fb3d193d72e3804292697d73d3aab Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 5 Jul 2022 21:29:01 +0200
+Subject: [PATCH v2 2/4] ARM: DTS: qcom: add rpmcc missing clocks for
+ apq/ipq8064 and msm8660
+
+Add missing rpmcc pxo and cxo clock for apq8064, ipq8064 and
+msm8660 dtsi.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+---
+ arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++
+ arch/arm/boot/dts/qcom-msm8660.dtsi | 4 +++-
+ 3 files changed, 7 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
+@@ -862,6 +862,8 @@
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
+ #clock-cells = <1>;
++ clocks = <&pxo_board>, <&cxo_board>;
++ clock-names = "pxo", "cxo";
+ };
+
+ regulators {
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -1074,6 +1074,8 @@
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
++ clocks = <&pxo_board>;
++ clock-names = "pxo";
+ };
+ };
+
+--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
++++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
+@@ -56,7 +56,7 @@
+ clock-frequency = <19200000>;
+ };
+
+- pxo_board {
++ pxo_board: pxo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+@@ -420,6 +420,8 @@
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
+ #clock-cells = <1>;
++ clocks = <&pxo_board>;
++ clock-names = "pxo";
+ };
+
+ pm8901-regulators {
--- /dev/null
+From 3d8c0e94a792ae62fa0495ac940c9850a059afc2 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 5 Jul 2022 21:39:18 +0200
+Subject: [PATCH v2 3/4] clk: qcom: clk-rpm: convert to parent_data API
+
+Convert clk-rpm driver to parent_data API.
+We keep the old pxo/cxo_board parent naming to keep compatibility with
+old DT and we use the new pxo/cxo for new implementation where these
+clock are defined in DTS.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++--------
+ 1 file changed, 16 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/qcom/clk-rpm.c
++++ b/drivers/clk/qcom/clk-rpm.c
+@@ -23,6 +23,14 @@
+ #define QCOM_RPM_SCALING_ENABLE_ID 0x2
+ #define QCOM_RPM_XO_MODE_ON 0x2
+
++static const struct clk_parent_data gcc_pxo[] = {
++ { .fw_name = "pxo", .name = "pxo_board" },
++};
++
++static const struct clk_parent_data gcc_cxo[] = {
++ { .fw_name = "cxo", .name = "cxo_board" },
++};
++
+ #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
+ static struct clk_rpm _platform##_##_active; \
+ static struct clk_rpm _platform##_##_name = { \
+@@ -32,8 +40,8 @@
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_ops, \
+ .name = #_name, \
+- .parent_names = (const char *[]){ "pxo_board" }, \
+- .num_parents = 1, \
++ .parent_data = gcc_pxo, \
++ .num_parents = ARRAY_SIZE(gcc_pxo), \
+ }, \
+ }; \
+ static struct clk_rpm _platform##_##_active = { \
+@@ -44,8 +52,8 @@
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_ops, \
+ .name = #_active, \
+- .parent_names = (const char *[]){ "pxo_board" }, \
+- .num_parents = 1, \
++ .parent_data = gcc_pxo, \
++ .num_parents = ARRAY_SIZE(gcc_pxo), \
+ }, \
+ }
+
+@@ -56,8 +64,8 @@
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_xo_ops, \
+ .name = #_name, \
+- .parent_names = (const char *[]){ "cxo_board" }, \
+- .num_parents = 1, \
++ .parent_data = gcc_cxo, \
++ .num_parents = ARRAY_SIZE(gcc_cxo), \
+ }, \
+ }
+
+@@ -68,8 +76,8 @@
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_fixed_ops, \
+ .name = #_name, \
+- .parent_names = (const char *[]){ "pxo" }, \
+- .num_parents = 1, \
++ .parent_data = gcc_pxo, \
++ .num_parents = ARRAY_SIZE(gcc_pxo), \
+ }, \
+ }
+
--- /dev/null
+From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 5 Jul 2022 18:30:18 +0200
+Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for
+ pxo and cxo
+
+Now that these clock are defined as fixed clk in dts, we can drop the
+register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -3384,14 +3384,6 @@ static int gcc_ipq806x_probe(struct plat
+ struct regmap *regmap;
+ int ret;
+
+- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
+- if (ret)
+- return ret;
+-
+- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
+- if (ret)
+- return ret;
+-
+ if (of_machine_is_compatible("qcom,ipq8065")) {
+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
projects / openwrt / staging / ansuel.git / commitdiff