drm/nouveau/gr/gf100-: virtualise init_ds_hww_esr_2
authorBen Skeggs <bskeggs@redhat.com>
Tue, 8 May 2018 10:39:46 +0000 (20:39 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 18 May 2018 05:01:22 +0000 (15:01 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c

index 0493483597edaa0d70fe7b37868b25317b739192..1f764df141bd0ad904ec80ae7bbf2ef2a38c8fb4 100644 (file)
@@ -2018,6 +2018,8 @@ gf100_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x400124, 0x00000002);
 
        gr->func->init_fecs_exceptions(gr);
+       if (gr->func->init_ds_hww_esr_2)
+               gr->func->init_ds_hww_esr_2(gr);
 
        nvkm_wr32(device, 0x404000, 0xc0000000);
        nvkm_wr32(device, 0x404600, 0xc0000000);
index 387938fa352b0bf23ce4e8bd8ea137848f5ac90a..ff3e265925c533e5c3b40fbdc16baa8d76c8f1d2 100644 (file)
@@ -131,6 +131,7 @@ struct gf100_gr_func {
        void (*init_bios_2)(struct gf100_gr *);
        void (*init_swdx_pes_mask)(struct gf100_gr *);
        void (*init_fecs_exceptions)(struct gf100_gr *);
+       void (*init_ds_hww_esr_2)(struct gf100_gr *);
        void (*init_ppc_exceptions)(struct gf100_gr *);
        void (*set_hww_esr_report_mask)(struct gf100_gr *);
        const struct gf100_gr_pack *mmio;
@@ -165,6 +166,7 @@ int gk20a_gr_init(struct gf100_gr *);
 
 int gm200_gr_rops(struct gf100_gr *);
 void gm200_gr_init_num_active_ltcs(struct gf100_gr *);
+void gm200_gr_init_ds_hww_esr_2(struct gf100_gr *);
 
 int gp100_gr_init(struct gf100_gr *);
 void gp100_gr_init_rop_active_fbps(struct gf100_gr *);
index a957993a0cc0ee6c9110be6b532122546586b642..b5994dca5d03f597b96136237e079eee93041934 100644 (file)
@@ -38,6 +38,14 @@ gm200_gr_rops(struct gf100_gr *gr)
        return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
 }
 
+void
+gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr)
+{
+       struct nvkm_device *device = gr->base.engine.subdev.device;
+       nvkm_wr32(device, 0x405848, 0xc0000000);
+       nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001);
+}
+
 void
 gm200_gr_init_num_active_ltcs(struct gf100_gr *gr)
 {
@@ -92,8 +100,7 @@ gm200_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x40013c, 0xffffffff);
        nvkm_wr32(device, 0x400124, 0x00000002);
        gr->func->init_fecs_exceptions(gr);
-       nvkm_wr32(device, 0x405848, 0xc0000000);
-       nvkm_wr32(device, 0x40584c, 0x00000001);
+       gr->func->init_ds_hww_esr_2(gr);
        nvkm_wr32(device, 0x404000, 0xc0000000);
        nvkm_wr32(device, 0x404600, 0xc0000000);
        nvkm_wr32(device, 0x408030, 0xc0000000);
@@ -194,6 +201,7 @@ gm200_gr = {
        .init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
+       .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
index 564b5b17b5033cfb1929a7166146e24acb7dda3b..676f58a9aceeb2707a9cb27d25cb1d9d11151d98 100644 (file)
@@ -70,8 +70,7 @@ gp100_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x40013c, 0xffffffff);
        nvkm_wr32(device, 0x400124, 0x00000002);
        gr->func->init_fecs_exceptions(gr);
-       nvkm_wr32(device, 0x405848, 0xc0000000);
-       nvkm_mask(device, 0x40584c, 0x00000000, 0x00000001);
+       gr->func->init_ds_hww_esr_2(gr);
        nvkm_wr32(device, 0x404000, 0xc0000000);
        nvkm_wr32(device, 0x404600, 0xc0000000);
        nvkm_wr32(device, 0x408030, 0xc0000000);
@@ -134,6 +133,7 @@ gp100_gr = {
        .init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
+       .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
index 04803fa7937a3115aadbe5da154729277c31486a..3694687c85dbf80d5a42e57a25cedf97b4b481e9 100644 (file)
@@ -50,6 +50,7 @@ gp102_gr = {
        .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
        .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
+       .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 3,
index c21cb8ae9a8bcb8dba593d3af100975b62e7c63a..c83ad01bad53bbb01ed68c0cb16c1a81ff5fee73 100644 (file)
@@ -36,6 +36,7 @@ gp107_gr = {
        .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
        .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
+       .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,
index 222b5b0c6e38935f60b238869a600e29e65139d6..8fef3b56cf8c2f5cd9b4b47465567d0140ac3810 100644 (file)
@@ -34,6 +34,7 @@ gp10b_gr = {
        .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
+       .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,