[ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code

Merge together the bits of the S3C2440 and S3C2442 clock code
that can be.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 79e2ea4adaf36defb9b1f863c1a0444146d2a9e0..184d804934c9b3d8c4d185a95b5c28208323083a 100644 (file)
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -111,14 +111,9 @@ static struct clk s3c2440_clk_ac97 = {
 
 static int s3c2440_clk_add(struct sys_device *sysdev)
 {
-       unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
-       unsigned long clkdivn;
+       struct clk *clock_upll;
        struct clk *clock_h;
        struct clk *clock_p;
-       struct clk *clock_upll;
-
-       printk("S3C2440: Clock Support, DVS %s\n",
-              (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
 
        clock_p = clk_get(NULL, "pclk");
        clock_h = clk_get(NULL, "hclk");
@@ -129,21 +124,6 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
                return -EINVAL;
        }
 
-       /* check rate of UPLL, and if it is near 96MHz, then change
-        * to using half the UPLL rate for the system */
-
-       if (clk_get_rate(clock_upll) > (94 * MHZ)) {
-               clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
-
-               mutex_lock(&clocks_mutex);
-
-               clkdivn = __raw_readl(S3C2410_CLKDIVN);
-               clkdivn |= S3C2440_CLKDIVN_UCLK;
-               __raw_writel(clkdivn, S3C2410_CLKDIVN);
-
-               mutex_unlock(&clocks_mutex);
-       }
-
        s3c2440_clk_cam.parent = clock_h;
        s3c2440_clk_ac97.parent = clock_p;
        s3c2440_clk_cam_upll.parent = clock_upll;

diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
index 5b9e830ac4d30a337529ad5e3609e786932f5954..2d030d439fe9ab8048a26438f4091566d6550f49 100644 (file)
--- a/arch/arm/mach-s3c2442/clock.c
+++ b/arch/arm/mach-s3c2442/clock.c
@@ -115,14 +115,9 @@ static struct clk s3c2442_clk_cam_upll = {
 
 static int s3c2442_clk_add(struct sys_device *sysdev)
 {
-       unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
-       unsigned long clkdivn;
+       struct clk *clock_upll;
        struct clk *clock_h;
        struct clk *clock_p;
-       struct clk *clock_upll;
-
-       printk("S3C2442: Clock Support, DVS %s\n",
-              (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
 
        clock_p = clk_get(NULL, "pclk");
        clock_h = clk_get(NULL, "hclk");
@@ -133,21 +128,6 @@ static int s3c2442_clk_add(struct sys_device *sysdev)
                return -EINVAL;
        }
 
-       /* check rate of UPLL, and if it is near 96MHz, then change
-        * to using half the UPLL rate for the system */
-
-       if (clk_get_rate(clock_upll) > (94 * MHZ)) {
-               clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
-
-               mutex_lock(&clocks_mutex);
-
-               clkdivn = __raw_readl(S3C2410_CLKDIVN);
-               clkdivn |= S3C2440_CLKDIVN_UCLK;
-               __raw_writel(clkdivn, S3C2410_CLKDIVN);
-
-               mutex_unlock(&clocks_mutex);
-       }
-
        s3c2442_clk_cam.parent = clock_h;
        s3c2442_clk_cam_upll.parent = clock_upll;
 

diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 8e5ccaa1f03cb8205cedd294d345065395bc40ec..131d20237dd7b3e8267436d2d4c8632d6862ac4f 100644 (file)
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -23,6 +23,7 @@ obj-y                         += clock.o
 
 obj-$(CONFIG_CPU_S3C244X)      += s3c244x.o
 obj-$(CONFIG_CPU_S3C244X)      += s3c244x-irq.o
+obj-$(CONFIG_CPU_S3C244X)      += s3c244x-clock.o
 obj-$(CONFIG_PM_SIMTEC)                += pm-simtec.o
 obj-$(CONFIG_PM)               += pm.o
 obj-$(CONFIG_PM)               += sleep.o

diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
new file mode 100644 (file)
index 0000000..0bf5e7f
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -0,0 +1,100 @@
+/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
+ *
+ * Copyright (c) 2004-2005,2008 Simtec Electronics
+ *     http://armlinux.simtec.co.uk/
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2440/S3C2442 Common clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/atomic.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/arch/regs-clock.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+static int s3c244x_clk_add(struct sys_device *sysdev)
+{
+       unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
+       unsigned long clkdivn;
+       struct clk *clock_upll;
+
+       printk("S3C244X: Clock Support, DVS %s\n",
+              (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
+
+       clock_upll = clk_get(NULL, "upll");
+       if (IS_ERR(clock_upll)) {
+               printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
+               return -ENOENT;
+       }
+
+       /* check rate of UPLL, and if it is near 96MHz, then change
+        * to using half the UPLL rate for the system */
+
+       if (clk_get_rate(clock_upll) > (94 * MHZ)) {
+               clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
+
+               mutex_lock(&clocks_mutex);
+
+               clkdivn = __raw_readl(S3C2410_CLKDIVN);
+               clkdivn |= S3C2440_CLKDIVN_UCLK;
+               __raw_writel(clkdivn, S3C2410_CLKDIVN);
+
+               mutex_unlock(&clocks_mutex);
+       }
+
+       return 0;
+}
+
+static struct sysdev_driver s3c2440_clk_driver = {
+       .add            = s3c244x_clk_add,
+};
+
+static int s3c2440_clk_init(void)
+{
+       return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
+}
+
+arch_initcall(s3c2440_clk_init);
+
+static struct sysdev_driver s3c2442_clk_driver = {
+       .add            = s3c244x_clk_add,
+};
+
+static int s3c2442_clk_init(void)
+{
+       return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
+}
+
+arch_initcall(s3c2442_clk_init);