drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active

On gen12, we no longer need to disable DC5/DC6 when when PG2 is in use
(which translates to cases where we're using VDSC on pipe A).

Bspec: 49193
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220231843.3127468-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6e25a13171615f35e9e4392d916a0b726dad029b..246e406bb385edbcf0d44d1c970c037136eff2b5 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -939,11 +939,17 @@ unlock:
 
 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 {
-       bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
-                                       SKL_DISP_PW_2);
+       enum i915_power_well_id high_pg;
 
-       drm_WARN_ONCE(&dev_priv->drm, pg2_enabled,
-                     "PG2 not disabled to enable DC5.\n");
+       /* Power wells at this level and above must be disabled for DC5 entry */
+       if (INTEL_GEN(dev_priv) >= 12)
+               high_pg = TGL_DISP_PW_3;
+       else
+               high_pg = SKL_DISP_PW_2;
+
+       drm_WARN_ONCE(&dev_priv->drm,
+                     intel_display_power_well_is_enabled(dev_priv, high_pg),
+                     "Power wells above platform's DC5 limit still enabled.\n");
 
        drm_WARN_ONCE(&dev_priv->drm,
                      (intel_de_read(dev_priv, DC_STATE_EN) &
@@ -2740,7 +2746,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        BIT_ULL(POWER_DOMAIN_INIT))
 
 #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (             \
-       TGL_PW_2_POWER_DOMAINS |                        \
+       TGL_PW_3_POWER_DOMAINS |                        \
        BIT_ULL(POWER_DOMAIN_MODESET) |                 \
        BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
        BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
@@ -3936,7 +3942,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
                .name = "power well 3",
                .domains = TGL_PW_3_POWER_DOMAINS,
                .ops = &hsw_power_well_ops,
-               .id = DISP_PW_ID_NONE,
+               .id = TGL_DISP_PW_3,
                {
                        .hsw.regs = &hsw_power_well_regs,
                        .hsw.idx = ICL_PW_CTL_IDX_PW_3,

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 601e000ffd0dc630357fab73d85b1aa621bf47e3..da64a5edae7ad14c75f3519bc14771ea8bf8f141 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,6 +100,7 @@ enum i915_power_well_id {
        SKL_DISP_PW_MISC_IO,
        SKL_DISP_PW_1,
        SKL_DISP_PW_2,
+       TGL_DISP_PW_3,
        SKL_DISP_DC_OFF,
 };