qed: Add API for configuring NVM attributes.
authorSudarsana Reddy Kalluru <skalluru@marvell.com>
Wed, 14 Aug 2019 08:11:52 +0000 (01:11 -0700)
committerDavid S. Miller <davem@davemloft.net>
Thu, 15 Aug 2019 19:54:44 +0000 (12:54 -0700)
The patch adds API for configuring the NVM config attributes using
Management FW (MFW) interfaces.

Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com>
Signed-off-by: Ariel Elior <aelior@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/qed_hsi.h
drivers/net/ethernet/qlogic/qed/qed_mcp.c
drivers/net/ethernet/qlogic/qed/qed_mcp.h

index e054f6c69e3a6c859f44b7c564c739736be607ed..557a12ef9815a935f2954d41b6a5730a6b7ad73c 100644 (file)
@@ -12580,6 +12580,8 @@ struct public_drv_mb {
 #define DRV_MSG_CODE_BW_UPDATE_ACK             0x32000000
 #define DRV_MSG_CODE_NIG_DRAIN                 0x30000000
 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK          0x3b000000
+#define DRV_MSG_CODE_GET_NVM_CFG_OPTION                0x003e0000
+#define DRV_MSG_CODE_SET_NVM_CFG_OPTION                0x003f0000
 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
 #define DRV_MSG_CODE_VF_DISABLED_DONE          0xc0000000
 #define DRV_MSG_CODE_CFG_VF_MSIX               0xc0010000
@@ -12748,6 +12750,21 @@ struct public_drv_mb {
 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE          0x00000002
 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK                0x00010000
 
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT           0
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK            0x0000FFFF
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT          16
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK           0x00010000
+#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT         17
+#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK          0x00020000
+#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT       18
+#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK                0x00040000
+#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT         19
+#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK          0x00080000
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT   20
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK    0x00100000
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT    24
+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK     0x0f000000
+
        u32 fw_mb_header;
 #define FW_MSG_CODE_MASK                       0xffff0000
 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
index 758702c1ce9c9f5c042abd4a6cb8b2441c609845..89462c4a50227540d6f0153b4e6d1688c57ecdae 100644 (file)
@@ -3750,3 +3750,35 @@ int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 
        return 0;
 }
+
+int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+                       u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
+                       u32 len)
+{
+       u32 mb_param = 0, resp, param;
+
+       QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
+       if (flags & QED_NVM_CFG_OPTION_ALL)
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1);
+       if (flags & QED_NVM_CFG_OPTION_INIT)
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
+       if (flags & QED_NVM_CFG_OPTION_COMMIT)
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1);
+       if (flags & QED_NVM_CFG_OPTION_FREE)
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
+       if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
+               QED_MFW_SET_FIELD(mb_param,
+                                 DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
+                                 entity_id);
+       }
+
+       return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
+                                 DRV_MSG_CODE_SET_NVM_CFG_OPTION,
+                                 mb_param, &resp, &param, len, (u32 *)p_buf);
+}
index e4f8fe4bd0626b9571f4ec0f1f983bb6b0d5667c..83649a82977b9e42615cfa3a85018e24dbf7dff9 100644 (file)
@@ -251,6 +251,12 @@ union qed_mfw_tlv_data {
        struct qed_mfw_tlv_iscsi iscsi;
 };
 
+#define QED_NVM_CFG_OPTION_ALL         BIT(0)
+#define QED_NVM_CFG_OPTION_INIT                BIT(1)
+#define QED_NVM_CFG_OPTION_COMMIT       BIT(2)
+#define QED_NVM_CFG_OPTION_FREE                BIT(3)
+#define QED_NVM_CFG_OPTION_ENTITY_SEL  BIT(4)
+
 /**
  * @brief - returns the link params of the hw function
  *
@@ -1202,4 +1208,18 @@ int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
  */
 int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 
+/**
+ * @brief Set NVM config attribute value.
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ * @param option_id
+ * @param entity_id
+ * @param flags
+ * @param p_buf
+ * @param len
+ */
+int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+                       u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
+                       u32 len);
 #endif