#include <arch_helpers.h>
#include <mmio.h>
#include <platform.h>
+#include <stdbool.h>
#include <string.h>
#include "pm_api_clock.h"
#include "pm_api_sys.h"
#include "pm_common.h"
#include "pm_ipi.h"
-#define CLK_NODE_MAX 6
+#define CLK_NODE_MAX U(6)
-#define CLK_PARENTS_ID_LEN 16
-#define CLK_TOPOLOGY_NODE_OFFSET 16
-#define CLK_TOPOLOGY_PAYLOAD_LEN 12
-#define CLK_PARENTS_PAYLOAD_LEN 12
-#define CLK_INIT_ENABLE_SHIFT 1
-#define CLK_TYPE_SHIFT 2
-#define CLK_CLKFLAGS_SHIFT 8
-#define CLK_TYPEFLAGS_SHIFT 24
+#define CLK_PARENTS_ID_LEN U(16)
+#define CLK_TOPOLOGY_NODE_OFFSET U(16)
+#define CLK_TOPOLOGY_PAYLOAD_LEN U(12)
+#define CLK_PARENTS_PAYLOAD_LEN U(12)
+#define CLK_INIT_ENABLE_SHIFT U(1)
+#define CLK_TYPE_SHIFT U(2)
+#define CLK_CLKFLAGS_SHIFT U(8)
+#define CLK_TYPEFLAGS_SHIFT U(24)
#define CLK_EXTERNAL_PARENT (PARENT_CLK_EXTERNAL << CLK_PARENTS_ID_LEN)
-#define NA_MULT 0
-#define NA_DIV 0
-#define NA_SHIFT 0
-#define NA_WIDTH 0
-#define NA_CLK_FLAGS 0
-#define NA_TYPE_FLAGS 0
+#define NA_MULT U(0)
+#define NA_DIV U(0)
+#define NA_SHIFT U(0)
+#define NA_WIDTH U(0)
+#define NA_CLK_FLAGS U(0)
+#define NA_TYPE_FLAGS U(0)
/* PLL nodes related definitions */
-#define PLL_PRESRC_MUX_SHIFT 20
-#define PLL_PRESRC_MUX_WIDTH 3
-#define PLL_POSTSRC_MUX_SHIFT 24
-#define PLL_POSTSRC_MUX_WIDTH 3
-#define PLL_DIV2_MUX_SHIFT 16
-#define PLL_DIV2_MUX_WIDTH 1
-#define PLL_BYPASS_MUX_SHIFT 3
-#define PLL_BYPASS_MUX_WIDTH 1
+#define PLL_PRESRC_MUX_SHIFT U(20)
+#define PLL_PRESRC_MUX_WIDTH U(3)
+#define PLL_POSTSRC_MUX_SHIFT U(24)
+#define PLL_POSTSRC_MUX_WIDTH U(3)
+#define PLL_DIV2_MUX_SHIFT U(16)
+#define PLL_DIV2_MUX_WIDTH U(1)
+#define PLL_BYPASS_MUX_SHIFT U(3)
+#define PLL_BYPASS_MUX_WIDTH U(1)
/* Peripheral nodes related definitions */
/* Peripheral Clocks */
-#define PERIPH_MUX_SHIFT 0
-#define PERIPH_MUX_WIDTH 3
-#define PERIPH_DIV1_SHIFT 8
-#define PERIPH_DIV1_WIDTH 6
-#define PERIPH_DIV2_SHIFT 16
-#define PERIPH_DIV2_WIDTH 6
-#define PERIPH_GATE_SHIFT 24
-#define PERIPH_GATE_WIDTH 1
+#define PERIPH_MUX_SHIFT U(0)
+#define PERIPH_MUX_WIDTH U(3)
+#define PERIPH_DIV1_SHIFT U(8)
+#define PERIPH_DIV1_WIDTH U(6)
+#define PERIPH_DIV2_SHIFT U(16)
+#define PERIPH_DIV2_WIDTH U(6)
+#define PERIPH_GATE_SHIFT U(24)
+#define PERIPH_GATE_WIDTH U(1)
-#define USB_GATE_SHIFT 25
+#define USB_GATE_SHIFT U(25)
/* External clock related definitions */
/* Clock control related definitions */
#define BIT_MASK(x, y) (((1U << (y)) - 1) << (x))
-#define ISPLL(id) (((id) == CLK_APLL_INT || \
- (id) == CLK_DPLL_INT || \
- (id) == CLK_VPLL_INT || \
- (id) == CLK_IOPLL_INT || \
- (id) == CLK_RPLL_INT) ? 1 : 0)
+#define ISPLL(id) (id == CLK_APLL_INT || \
+ id == CLK_DPLL_INT || \
+ id == CLK_VPLL_INT || \
+ id == CLK_IOPLL_INT || \
+ id == CLK_RPLL_INT)
+
#define PLLCTRL_BP_MASK BIT(3)
-#define PLLCTRL_RESET_MASK 1
-#define PLL_FRAC_OFFSET 8
-#define PLL_FRAC_MODE 1
-#define PLL_INT_MODE 0
-#define PLL_FRAC_MODE_MASK 0x80000000
-#define PLL_FRAC_MODE_SHIFT 31
-#define PLL_FRAC_DATA_MASK 0xFFFF
-#define PLL_FRAC_DATA_SHIFT 0
-#define PLL_FBDIV_MASK 0x7F00
-#define PLL_FBDIV_WIDTH 7
-#define PLL_FBDIV_SHIFT 8
-
-#define CLK_PLL_RESET_ASSERT 1
-#define CLK_PLL_RESET_RELEASE 2
+#define PLLCTRL_RESET_MASK U(1)
+#define PLL_FRAC_OFFSET U(8)
+#define PLL_FRAC_MODE U(1)
+#define PLL_INT_MODE U(0)
+#define PLL_FRAC_MODE_MASK U(0x80000000)
+#define PLL_FRAC_MODE_SHIFT U(31)
+#define PLL_FRAC_DATA_MASK U(0xFFFF)
+#define PLL_FRAC_DATA_SHIFT U(0)
+#define PLL_FBDIV_MASK U(0x7F00)
+#define PLL_FBDIV_WIDTH U(7)
+#define PLL_FBDIV_SHIFT U(8)
+
+#define CLK_PLL_RESET_ASSERT U(1)
+#define CLK_PLL_RESET_RELEASE U(2)
#define CLK_PLL_RESET_PULSE (CLK_PLL_RESET_ASSERT | CLK_PLL_RESET_RELEASE)
/* Common topology definitions */
};
/* Array of clock which are invalid for this variant */
-uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB};
+static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB};
/* Array of clocks which needs to be enabled at init */
-uint32_t pm_clk_init_enable_list[] = {
+static uint32_t pm_clk_init_enable_list[] = {
CLK_ACPU,
CLK_DDR_REF,
};
*
* Return: Returns 1 if clock is valid else 0.
*/
-static unsigned int pm_clock_valid(unsigned int clock_id)
+static bool pm_clock_valid(unsigned int clock_id)
{
- int i;
+ unsigned int i;
for (i = 0; i < ARRAY_SIZE(pm_clk_invalid_list); i++)
if (pm_clk_invalid_list[i] == clock_id)
*/
static unsigned int pm_clock_init_enable(unsigned int clock_id)
{
- int i;
+ unsigned int i;
for (i = 0; i < ARRAY_SIZE(pm_clk_init_enable_list); i++)
if (pm_clk_init_enable_list[i] == clock_id)
if (index >= num_nodes)
return PM_RET_SUCCESS;
- for (i = 0; i < 3; i++) {
+ for (i = 0; i < 3U; i++) {
if ((index + i) == num_nodes)
break;
topology[i] = clock_nodes[index + i].type;
unsigned int index,
uint32_t *parents)
{
- int i;
+ unsigned int i;
int32_t *clk_parents;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_NOTSUPPORTED;
clk_parents = *clocks[clock_id].parents;
- if (!clk_parents)
+ if (clk_parents == NULL)
return PM_RET_ERROR_ARGS;
memset(parents, 0, CLK_PARENTS_PAYLOAD_LEN);
*
* This function is to bypass and reset PLL.
*/
-static inline void pm_api_pll_bypass_and_reset(unsigned int clock_id,
- unsigned int flag)
+static inline enum pm_ret_status
+pm_api_pll_bypass_and_reset(unsigned int clock_id, unsigned int flag)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
unsigned int reg, val;
int lockbit;
reg = clocks[clock_id].control_reg;
if (flag & CLK_PLL_RESET_ASSERT) {
- pm_mmio_write(reg, PLLCTRL_BP_MASK, PLLCTRL_BP_MASK);
- pm_mmio_write(reg, PLLCTRL_RESET_MASK, PLLCTRL_RESET_MASK);
+ ret = pm_mmio_write(reg, PLLCTRL_BP_MASK, PLLCTRL_BP_MASK);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
+ ret = pm_mmio_write(reg, PLLCTRL_RESET_MASK,
+ PLLCTRL_RESET_MASK);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
}
if (flag & CLK_PLL_RESET_RELEASE) {
- pm_mmio_write(reg, PLLCTRL_RESET_MASK, ~PLLCTRL_RESET_MASK);
+ ret = pm_mmio_write(reg, PLLCTRL_RESET_MASK,
+ ~PLLCTRL_RESET_MASK);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
lockbit = pll_get_lockbit(clock_id);
do {
- pm_mmio_read(clocks[clock_id].status_reg, &val);
+ ret = pm_mmio_read(clocks[clock_id].status_reg, &val);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
} while ((lockbit >= 0) && !(val & (1 << lockbit)));
- pm_mmio_write(reg, PLLCTRL_BP_MASK,
+ ret = pm_mmio_write(reg, PLLCTRL_BP_MASK,
~(unsigned int)PLLCTRL_BP_MASK);
}
+ return ret;
}
/**
static enum pm_ret_status pm_api_clk_enable_disable(unsigned int clock_id,
unsigned int enable)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
struct pm_clock_node *nodes = *clocks[clock_id].nodes;
uint8_t num_nodes = clocks[clock_id].num_nodes;
unsigned int reg, val;
- int i = 0, offset = NA_SHIFT, width = NA_WIDTH;
+ uint8_t i = 0;
+ uint8_t offset = NA_SHIFT, width = NA_WIDTH;
if (clock_id == CLK_GEM0_TX || clock_id == CLK_GEM1_TX ||
clock_id == CLK_GEM2_TX || clock_id == CLK_GEM3_TX)
if (width == NA_WIDTH)
return PM_RET_ERROR_NOTSUPPORTED;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
if ((val & BIT_MASK(offset, width)) == enable)
return PM_RET_SUCCESS;
- if (enable)
- val |= BIT_MASK(offset, width);
- else
+ if (enable == 0)
val &= ~(BIT_MASK(offset, width));
+ else
+ val |= BIT_MASK(offset, width);
- pm_mmio_write(reg, BIT_MASK(offset, width), val);
+ ret = pm_mmio_write(reg, BIT_MASK(offset, width), val);
- return PM_RET_SUCCESS;
+ return ret;
}
/**
*/
enum pm_ret_status pm_api_clock_enable(unsigned int clock_id)
{
- int ret = PM_RET_SUCCESS;
+ enum pm_ret_status ret = PM_RET_SUCCESS;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
return PM_RET_ERROR_NOTSUPPORTED;
if (ISPLL(clock_id))
- pm_api_pll_bypass_and_reset(clock_id, CLK_PLL_RESET_PULSE);
+ ret = pm_api_pll_bypass_and_reset(clock_id,
+ CLK_PLL_RESET_PULSE);
else
ret = pm_api_clk_enable_disable(clock_id, 1);
enum pm_ret_status pm_api_clock_disable(unsigned int clock_id)
{
- int ret = PM_RET_SUCCESS;
+ enum pm_ret_status ret = PM_RET_SUCCESS;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
return PM_RET_ERROR_NOTSUPPORTED;
if (ISPLL(clock_id))
- pm_api_pll_bypass_and_reset(clock_id, CLK_PLL_RESET_ASSERT);
+ ret = pm_api_pll_bypass_and_reset(clock_id,
+ CLK_PLL_RESET_ASSERT);
else
ret = pm_api_clk_enable_disable(clock_id, 0);
*
* This function is to check state of PLL.
*/
-static inline void pm_api_get_pll_state(unsigned int clock_id,
+static inline enum pm_ret_status pm_api_get_pll_state(unsigned int clock_id,
unsigned int *state)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
unsigned int reg, val;
reg = clocks[clock_id].control_reg;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
/* state:
* 1 - PLL is enabled
* 0 - PLL is in reset state
*/
*state = !(val & PLLCTRL_RESET_MASK);
+ return ret;
}
/**
static enum pm_ret_status pm_api_get_clk_state(unsigned int clock_id,
unsigned int *state)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
struct pm_clock_node *nodes = *clocks[clock_id].nodes;
uint8_t num_nodes = clocks[clock_id].num_nodes;
unsigned int reg, val;
- int i = 0, offset = NA_SHIFT, width = NA_WIDTH;
+ uint8_t i = 0;
+ uint8_t offset = NA_SHIFT, width = NA_WIDTH;
reg = clocks[clock_id].control_reg;
if (width == NA_WIDTH)
return PM_RET_ERROR_NOTSUPPORTED;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
*state = (val & BIT_MASK(offset, width)) >> offset;
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
unsigned int *state)
{
- int ret = PM_RET_SUCCESS;
+ enum pm_ret_status ret = PM_RET_SUCCESS;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
return PM_RET_ERROR_NOTSUPPORTED;
if (ISPLL(clock_id))
- pm_api_get_pll_state(clock_id, state);
+ ret = pm_api_get_pll_state(clock_id, state);
else
ret = pm_api_get_clk_state(clock_id, state);
static enum pm_ret_status pm_api_clk_set_divider(unsigned int clock_id,
uint32_t divider)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
struct pm_clock_node *nodes;
uint8_t num_nodes;
uint16_t div1, div2;
unsigned int reg, mask = 0, val = 0, i;
- unsigned int div1_width = NA_WIDTH, div1_offset = NA_SHIFT;
- unsigned int div2_width = NA_WIDTH, div2_offset = NA_SHIFT;
+ uint8_t div1_width = NA_WIDTH, div1_offset = NA_SHIFT;
+ uint8_t div2_width = NA_WIDTH, div2_offset = NA_SHIFT;
- div1 = divider & 0xFFFF;
- div2 = (divider >> 16) & 0xFFFF;
+ div1 = (uint16_t)(divider & 0xFFFFU);
+ div2 = (uint16_t)((divider >> 16) & 0xFFFFU);
reg = clocks[clock_id].control_reg;
val |= div2 << div2_offset;
mask |= BIT_MASK(div2_offset, div2_width);
}
- pm_mmio_write(reg, mask, val);
+ ret = pm_mmio_write(reg, mask, val);
- return PM_RET_SUCCESS;
+ return ret;
}
-enum pm_ret_status pm_api_pll_set_divider(unsigned int clock_id,
+static enum pm_ret_status pm_api_pll_set_divider(unsigned int clock_id,
unsigned int divider)
{
unsigned int reg = clocks[clock_id].control_reg;
enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
unsigned int divider)
{
- int ret;
+ enum pm_ret_status ret;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
static enum pm_ret_status pm_api_clk_get_divider(unsigned int clock_id,
uint32_t *divider)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
struct pm_clock_node *nodes;
uint8_t num_nodes;
unsigned int reg, val, i, div1 = 0, div2 = 0;
- unsigned int div1_width = NA_WIDTH, div1_offset = NA_SHIFT;
- unsigned int div2_width = NA_WIDTH, div2_offset = NA_SHIFT;
+ uint8_t div1_width = NA_WIDTH, div1_offset = NA_SHIFT;
+ uint8_t div2_width = NA_WIDTH, div2_offset = NA_SHIFT;
reg = clocks[clock_id].control_reg;
nodes++;
}
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
if (div1_width == NA_WIDTH)
return PM_RET_ERROR_ARGS;
*divider = div1 | (div2 << 16);
- return PM_RET_SUCCESS;
+ return ret;
}
-enum pm_ret_status pm_api_pll_get_divider(unsigned int clock_id,
+static enum pm_ret_status pm_api_pll_get_divider(unsigned int clock_id,
unsigned int *divider)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
unsigned int reg, val;
reg = clocks[clock_id].control_reg;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
*divider = (val & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
unsigned int *divider)
{
- int ret;
+ enum pm_ret_status ret;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id,
unsigned int parent_idx)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
struct pm_clock_node *nodes;
uint8_t num_nodes;
unsigned int reg, val;
int32_t *clk_parents;
- int i = 0, offset = NA_SHIFT, width = NA_WIDTH;
+ unsigned int i = 0;
+ uint8_t offset = NA_SHIFT, width = NA_WIDTH;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
reg = clocks[clock_id].control_reg;
val = parent_idx << offset;
- pm_mmio_write(reg, BIT_MASK(offset, width), val);
+ ret = pm_mmio_write(reg, BIT_MASK(offset, width), val);
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id,
unsigned int *parent_idx)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
struct pm_clock_node *nodes;
uint8_t num_nodes;
unsigned int reg, val;
- int i = 0, offset = NA_SHIFT, width = NA_WIDTH;
+ uint8_t i = 0, offset = NA_SHIFT, width = NA_WIDTH;
if (!pm_clock_valid(clock_id))
return PM_RET_ERROR_ARGS;
return PM_RET_ERROR_NOTSUPPORTED;
reg = clocks[clock_id].control_reg;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
val >>= offset;
val &= ((1U << width) - 1);
*parent_idx = val;
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll,
unsigned int mode)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
unsigned int reg;
if (!pm_clock_valid(pll))
reg = clocks[pll].control_reg + PLL_FRAC_OFFSET;
- pm_mmio_write(reg, PLL_FRAC_MODE_MASK, mode << PLL_FRAC_MODE_SHIFT);
+ ret = pm_mmio_write(reg, PLL_FRAC_MODE_MASK,
+ mode << PLL_FRAC_MODE_SHIFT);
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll,
unsigned int *mode)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
unsigned int val, reg;
if (!pm_clock_valid(pll))
reg = clocks[pll].control_reg + PLL_FRAC_OFFSET;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
val = val & PLL_FRAC_MODE_MASK;
- if (val)
- *mode = PLL_FRAC_MODE;
- else
+ if (val == 0)
*mode = PLL_INT_MODE;
+ else
+ *mode = PLL_FRAC_MODE;
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll,
unsigned int data)
{
- unsigned int val, reg, mode;
+ enum pm_ret_status ret = PM_RET_SUCCESS;
+ unsigned int val, reg, mode = 0;
if (!pm_clock_valid(pll))
return PM_RET_ERROR_ARGS;
if (!ISPLL(pll))
return PM_RET_ERROR_NOTSUPPORTED;
- pm_api_clk_get_pll_mode(pll, &mode);
+ ret = pm_api_clk_get_pll_mode(pll, &mode);
+ if (ret != PM_RET_SUCCESS)
+ return ret;
if (mode == PLL_FRAC_MODE) {
reg = clocks[pll].control_reg + PLL_FRAC_OFFSET;
val = data << PLL_FRAC_DATA_SHIFT;
- pm_mmio_write(reg, PLL_FRAC_DATA_MASK, val);
+ ret = pm_mmio_write(reg, PLL_FRAC_DATA_MASK, val);
} else {
return PM_RET_ERROR_ARGS;
}
- return PM_RET_SUCCESS;
+ return ret;
}
/**
enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll,
unsigned int *data)
{
+ enum pm_ret_status ret = PM_RET_SUCCESS;
unsigned int val, reg;
if (!pm_clock_valid(pll))
reg = clocks[pll].control_reg + PLL_FRAC_OFFSET;
- pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(reg, &val);
*data = (val & PLL_FRAC_DATA_MASK);
- return PM_RET_SUCCESS;
+ return ret;
}
#include <utils_def.h>
#include "pm_common.h"
-#define CLK_NAME_LEN 15
-#define MAX_PARENTS 100
+#define CLK_NAME_LEN U(15)
+#define MAX_PARENTS U(100)
#define CLK_NA_PARENT -1
#define CLK_DUMMY_PARENT -2
/* Flags for parent id */
-#define PARENT_CLK_SELF 0
-#define PARENT_CLK_NODE1 1
-#define PARENT_CLK_NODE2 2
-#define PARENT_CLK_NODE3 3
-#define PARENT_CLK_NODE4 4
-#define PARENT_CLK_EXTERNAL 5
-#define PARENT_CLK_MIO0_MIO77 6
+#define PARENT_CLK_SELF U(0)
+#define PARENT_CLK_NODE1 U(1)
+#define PARENT_CLK_NODE2 U(2)
+#define PARENT_CLK_NODE3 U(3)
+#define PARENT_CLK_NODE4 U(4)
+#define PARENT_CLK_EXTERNAL U(5)
+#define PARENT_CLK_MIO0_MIO77 U(6)
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
#define END_OF_CLK "END_OF_CLK"
-enum clock_ids {
+//CLock Ids
+enum {
CLK_IOPLL,
CLK_RPLL,
CLK_APLL,
CLK_VPLL_POST_SRC,
CLK_CAN0_MIO,
CLK_CAN1_MIO,
- CLK_MAX_OUTPUT_CLK,
+ END_OF_OUTPUT_CLKS,
};
-enum external_clk_ids {
- EXT_CLK_PSS_REF = CLK_MAX_OUTPUT_CLK,
+#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
+
+//External clock ids
+enum {
+ EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
EXT_CLK_VIDEO,
EXT_CLK_PSS_ALT_REF,
EXT_CLK_AUX_REF,
EXT_CLK_MIO75,
EXT_CLK_MIO76,
EXT_CLK_MIO77,
- CLK_MAX,
+ END_OF_CLKS,
};
-enum clk_type {
- CLK_TYPE_OUTPUT,
- CLK_TYPE_EXTERNAL,
-};
+#define CLK_MAX (unsigned int)(END_OF_CLKS)
+
+//CLock types
+#define CLK_TYPE_OUTPUT 0U
+#define CLK_TYPE_EXTERNAL 1U
+
+//Topology types
+#define TYPE_INVALID 0U
+#define TYPE_MUX 1U
+#define TYPE_PLL 2U
+#define TYPE_FIXEDFACTOR 3U
+#define TYPE_DIV1 4U
+#define TYPE_DIV2 5U
+#define TYPE_GATE 6U
-enum topology_type {
- TYPE_INVALID,
- TYPE_MUX,
- TYPE_PLL,
- TYPE_FIXEDFACTOR,
- TYPE_DIV1,
- TYPE_DIV2,
- TYPE_GATE,
-};
enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
val &= ZYNQMP_SLSPLIT_MASK;
- if (val)
- *mode = PM_RPU_MODE_SPLIT;
- else
+ if (val == 0)
*mode = PM_RPU_MODE_LOCKSTEP;
+ else
+ *mode = PM_RPU_MODE_SPLIT;
return PM_RET_SUCCESS;
}
unsigned int value)
{
unsigned int val, mask, shift;
- int ret;
+ enum pm_ret_status ret;
if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE)
return PM_RET_ERROR_ARGS;
if (value == PM_SGMII_DISABLE) {
mask = GEM_SGMII_MASK << GEM_CLK_CTRL_OFFSET * shift;
- ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0);
+ ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0U);
} else {
/* Tie the GEM PCS Signal Detect to 1 */
mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
- if (ret)
+ if (ret != PM_RET_SUCCESS)
return ret;
/* Set the GEM to SGMII mode */
unsigned int type)
{
unsigned int mask, val;
- int ret;
+ enum pm_ret_status ret;
if (nid == NODE_SD_0) {
mask = ZYNQMP_SD0_DLL_RST_MASK;
case PM_DLL_RESET_ASSERT:
case PM_DLL_RESET_PULSE:
ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val);
- if (ret)
+ if (ret != PM_RET_SUCCESS)
return ret;
if (type == PM_DLL_RESET_ASSERT)
break;
default:
ret = PM_RET_ERROR_ARGS;
+ break;
}
return ret;
unsigned int value)
{
unsigned int shift;
- int ret;
+ enum pm_ret_status ret;
if (nid == NODE_SD_0)
shift = 0;
return PM_RET_ERROR_ARGS;
ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
- if (ret)
+ if (ret != PM_RET_SUCCESS)
return ret;
if (type == PM_TAPDELAY_INPUT) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
- ZYNQMP_SD_ITAPCHGWIN_MASK << shift,
- ZYNQMP_SD_ITAPCHGWIN << shift);
- if (ret)
+ (ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
+ (ZYNQMP_SD_ITAPCHGWIN << shift));
+ if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
- ZYNQMP_SD_ITAPDLYENA_MASK << shift,
- ZYNQMP_SD_ITAPDLYENA << shift);
- if (ret)
+ (ZYNQMP_SD_ITAPDLYENA_MASK << shift),
+ (ZYNQMP_SD_ITAPDLYENA << shift));
+ if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
- ZYNQMP_SD_ITAPDLYSEL_MASK << shift,
- value << shift);
- if (ret)
+ (ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
+ (value << shift));
+ if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
- ZYNQMP_SD_ITAPCHGWIN_MASK << shift, 0);
+ (ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
- ZYNQMP_SD_OTAPDLYENA_MASK << shift,
- ZYNQMP_SD_OTAPDLYENA << shift);
- if (ret)
+ (ZYNQMP_SD_OTAPDLYENA_MASK << shift),
+ (ZYNQMP_SD_OTAPDLYENA << shift));
+ if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
- ZYNQMP_SD_OTAPDLYSEL_MASK << shift,
- value << shift);
+ (ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
+ (value << shift));
} else {
ret = PM_RET_ERROR_ARGS;
}
reset_release:
- ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
- if (ret)
- return ret;
-
+ pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
return ret;
}
if (index >= GGS_NUM_REGS)
return PM_RET_ERROR_ARGS;
- return pm_mmio_write(GGS_BASEADDR + (index << 2), 0xFFFFFFFF, value);
+ return pm_mmio_write(GGS_BASEADDR + (index << 2),
+ 0xFFFFFFFFU, value);
}
/**
if (index >= PGGS_NUM_REGS)
return PM_RET_ERROR_ARGS;
- return pm_mmio_write(PGGS_BASEADDR + (index << 2), 0xFFFFFFFF, value);
+ return pm_mmio_write(PGGS_BASEADDR + (index << 2),
+ 0xFFFFFFFFU, value);
}
/**
unsigned int arg2,
unsigned int *value)
{
- int ret;
+ enum pm_ret_status ret;
switch (ioctl_id) {
case IOCTL_GET_RPU_OPER_MODE:
break;
default:
ret = PM_RET_ERROR_NOTSUPPORTED;
+ break;
}
return ret;
#include "pm_common.h"
-enum pm_ioctl_id {
+//ioctl id
+enum {
IOCTL_GET_RPU_OPER_MODE,
IOCTL_SET_RPU_OPER_MODE,
IOCTL_RPU_BOOT_ADDR_CONFIG,
IOCTL_READ_PGGS,
};
-enum rpu_oper_mode {
- PM_RPU_MODE_LOCKSTEP,
- PM_RPU_MODE_SPLIT,
-};
+//RPU operation mode
+#define PM_RPU_MODE_LOCKSTEP 0U
+#define PM_RPU_MODE_SPLIT 1U
-enum rpu_boot_mem {
- PM_RPU_BOOTMEM_LOVEC,
- PM_RPU_BOOTMEM_HIVEC,
-};
+//RPU boot mem
+#define PM_RPU_BOOTMEM_LOVEC 0U
+#define PM_RPU_BOOTMEM_HIVEC 1U
-enum rpu_tcm_comb {
- PM_RPU_TCM_SPLIT,
- PM_RPU_TCM_COMB,
-};
+//RPU tcm mpde
+#define PM_RPU_TCM_SPLIT 0U
+#define PM_RPU_TCM_COMB 1U
-enum tap_delay_signal_type {
- PM_TAPDELAY_NAND_DQS_IN,
- PM_TAPDELAY_NAND_DQS_OUT,
- PM_TAPDELAY_QSPI,
- PM_TAPDELAY_MAX,
-};
+//tap delay signal type
+#define PM_TAPDELAY_NAND_DQS_IN 0U
+#define PM_TAPDELAY_NAND_DQS_OUT 1U
+#define PM_TAPDELAY_QSPI 2U
+#define PM_TAPDELAY_MAX 3U
-enum tap_delay_bypass_ctrl {
- PM_TAPDELAY_BYPASS_DISABLE,
- PM_TAPDELAY_BYPASS_ENABLE,
-};
+//tap delay bypass
+#define PM_TAPDELAY_BYPASS_DISABLE 0U
+#define PM_TAPDELAY_BYPASS_ENABLE 1U
-enum sgmii_mode {
- PM_SGMII_DISABLE,
- PM_SGMII_ENABLE,
-};
+//sgmii mode
+#define PM_SGMII_DISABLE 0U
+#define PM_SGMII_ENABLE 1U
enum tap_delay_type {
PM_TAPDELAY_INPUT,
PM_TAPDELAY_OUTPUT,
};
-enum dll_reset_type {
- PM_DLL_RESET_ASSERT,
- PM_DLL_RESET_RELEASE,
- PM_DLL_RESET_PULSE,
-};
+//dll reset type
+#define PM_DLL_RESET_ASSERT 0U
+#define PM_DLL_RESET_RELEASE 1U
+#define PM_DLL_RESET_PULSE 2U
enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
unsigned int ioctl_id,
#include "pm_common.h"
#include "pm_ipi.h"
-#define PINCTRL_FUNCTION_MASK 0xFE
-#define PINCTRL_VOLTAGE_STATUS_MASK 0x01
-#define NFUNCS_PER_PIN 13
-#define PINCTRL_NUM_MIOS 78
-#define MAX_PIN_PER_REG 26
-#define PINCTRL_BANK_ADDR_STEP 28
-
-#define PINCTRL_DRVSTRN0_REG_OFFSET 0
-#define PINCTRL_DRVSTRN1_REG_OFFSET 4
-#define PINCTRL_SCHCMOS_REG_OFFSET 8
-#define PINCTRL_PULLCTRL_REG_OFFSET 12
-#define PINCTRL_PULLSTAT_REG_OFFSET 16
-#define PINCTRL_SLEWCTRL_REG_OFFSET 20
-#define PINCTRL_VOLTAGE_STAT_REG_OFFSET 24
-
-#define IOU_SLCR_BANK1_CTRL5 0XFF180164
-
-#define PINCTRL_CFG_ADDR_OFFSET(addr, reg, pin) \
+#define PINCTRL_FUNCTION_MASK U(0xFE)
+#define PINCTRL_VOLTAGE_STATUS_MASK U(0x01)
+#define NFUNCS_PER_PIN U(13)
+#define PINCTRL_NUM_MIOS U(78)
+#define MAX_PIN_PER_REG U(26)
+#define PINCTRL_BANK_ADDR_STEP U(28)
+
+#define PINCTRL_DRVSTRN0_REG_OFFSET U(0)
+#define PINCTRL_DRVSTRN1_REG_OFFSET U(4)
+#define PINCTRL_SCHCMOS_REG_OFFSET U(8)
+#define PINCTRL_PULLCTRL_REG_OFFSET U(12)
+#define PINCTRL_PULLSTAT_REG_OFFSET U(16)
+#define PINCTRL_SLEWCTRL_REG_OFFSET U(20)
+#define PINCTRL_VOLTAGE_STAT_REG_OFFSET U(24)
+
+#define IOU_SLCR_BANK1_CTRL5 U(0XFF180164)
+
+#define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin) \
((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \
- ((pin) / MAX_PIN_PER_REG) + (reg))
+ ((miopin) / MAX_PIN_PER_REG) + (reg))
-#define PINCTRL_PIN_OFFSET(pin) \
- ((pin) - (MAX_PIN_PER_REG * ((pin) / MAX_PIN_PER_REG)))
+#define PINCTRL_PIN_OFFSET(_miopin) \
+ ((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG)))
-#define PINCTRL_REGVAL_TO_PIN_CONFIG(pin, value) \
- (((value) >> PINCTRL_PIN_OFFSET(pin)) & 0x1)
+#define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val) \
+ (((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1)
static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = {
0x02, 0x04, 0x08, 0x10, 0x18,
};
/* Max groups for one pin */
-#define MAX_PIN_GROUPS 13
+#define MAX_PIN_GROUPS U(13)
struct zynqmp_pin_group {
uint16_t (*groups)[];
*ngroups = 0;
grps = *pinctrl_functions[fid].groups;
- if (!grps)
+ if (grps == NULL)
return PM_RET_SUCCESS;
while (grps[i++] != (uint16_t)END_OF_GROUPS)
unsigned int index,
uint16_t *groups)
{
- int i;
+ unsigned int i;
uint16_t *grps;
if (fid >= MAX_FUNCTION)
memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = *pinctrl_functions[fid].groups;
- if (!grps)
+ if (grps == NULL)
return PM_RET_SUCCESS;
/* Skip groups till index */
unsigned int index,
uint16_t *groups)
{
- int i;
+ unsigned int i;
uint16_t *grps;
if (pin >= MAX_PIN)
enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
unsigned int *id)
{
- int i = 0, j = 0, ret = PM_RET_SUCCESS;
- unsigned int reg, val, gid;
+ unsigned int i = 0, j = 0;
+ enum pm_ret_status ret = PM_RET_SUCCESS;
+ unsigned int ctrlreg, val, gid;
uint16_t *grps;
- reg = IOU_SLCR_BASEADDR + 4 * pin;
- ret = pm_mmio_read(reg, &val);
- if (ret)
+ ctrlreg = IOU_SLCR_BASEADDR + 4U * pin;
+ ret = pm_mmio_read(ctrlreg, &val);
+ if (ret != PM_RET_SUCCESS)
return ret;
val &= PINCTRL_FUNCTION_MASK;
for (i = 0; i < MAX_FUNCTION; i++) {
grps = *pinctrl_functions[i].groups;
- if (!grps)
+ if (grps == NULL)
continue;
if (val != pinctrl_functions[i].regval)
continue;
unsigned int fid)
{
int i, j;
- unsigned int reg, val;
+ unsigned int ctrlreg, val;
uint16_t *pgrps, *fgrps;
- reg = IOU_SLCR_BASEADDR + 4 * pin;
+ ctrlreg = IOU_SLCR_BASEADDR + 4U * pin;
val = pinctrl_functions[fid].regval;
for (i = 0; i < NFUNCS_PER_PIN; i++)
return PM_RET_ERROR_NOTSUPPORTED;
match:
- return pm_mmio_write(reg, PINCTRL_FUNCTION_MASK, val);
+ return pm_mmio_write(ctrlreg, PINCTRL_FUNCTION_MASK, val);
}
/**
unsigned int param,
unsigned int value)
{
- int ret;
- unsigned int reg, mask, val, offset;
+ enum pm_ret_status ret;
+ unsigned int ctrlreg, mask, val, offset;
if (param >= PINCTRL_CONFIG_MAX)
return PM_RET_ERROR_NOTSUPPORTED;
value != PINCTRL_SLEW_RATE_SLOW)
return PM_RET_ERROR_ARGS;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_SLEWCTRL_REG_OFFSET,
pin);
val = value << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(reg, mask, val);
+ ret = pm_mmio_write(ctrlreg, mask, val);
break;
case PINCTRL_CONFIG_BIAS_STATUS:
if (value != PINCTRL_BIAS_ENABLE &&
value != PINCTRL_BIAS_DISABLE)
return PM_RET_ERROR_ARGS;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_PULLSTAT_REG_OFFSET,
pin);
offset = PINCTRL_PIN_OFFSET(pin);
- if (reg == IOU_SLCR_BANK1_CTRL5)
- offset = (offset < 12) ? (offset + 14) : (offset - 12);
+ if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
+ offset = (offset < 12U) ?
+ (offset + 14U) : (offset - 12U);
val = value << offset;
mask = 1 << offset;
- ret = pm_mmio_write(reg, mask, val);
+ ret = pm_mmio_write(ctrlreg, mask, val);
break;
case PINCTRL_CONFIG_PULL_CTRL:
value != PINCTRL_BIAS_PULL_UP)
return PM_RET_ERROR_ARGS;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_PULLSTAT_REG_OFFSET,
pin);
offset = PINCTRL_PIN_OFFSET(pin);
- if (reg == IOU_SLCR_BANK1_CTRL5)
- offset = (offset < 12) ? (offset + 14) : (offset - 12);
+ if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
+ offset = (offset < 12U) ?
+ (offset + 14U) : (offset - 12U);
val = PINCTRL_BIAS_ENABLE << offset;
- ret = pm_mmio_write(reg, 1 << offset, val);
- if (ret)
+ ret = pm_mmio_write(ctrlreg, 1 << offset, val);
+ if (ret != PM_RET_SUCCESS)
return ret;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_PULLCTRL_REG_OFFSET,
pin);
val = value << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(reg, mask, val);
+ ret = pm_mmio_write(ctrlreg, mask, val);
break;
case PINCTRL_CONFIG_SCHMITT_CMOS:
if (value != PINCTRL_INPUT_TYPE_CMOS &&
value != PINCTRL_INPUT_TYPE_SCHMITT)
return PM_RET_ERROR_ARGS;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_SCHCMOS_REG_OFFSET,
pin);
val = value << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(reg, mask, val);
+ ret = pm_mmio_write(ctrlreg, mask, val);
break;
case PINCTRL_CONFIG_DRIVE_STRENGTH:
if (value > PINCTRL_DRIVE_STRENGTH_12MA)
return PM_RET_ERROR_ARGS;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_DRVSTRN0_REG_OFFSET,
pin);
val = (value >> 1) << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(reg, mask, val);
+ ret = pm_mmio_write(ctrlreg, mask, val);
if (ret)
return ret;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_DRVSTRN1_REG_OFFSET,
pin);
- val = (value & 0x01) << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(reg, mask, val);
+ val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin);
+ ret = pm_mmio_write(ctrlreg, mask, val);
break;
default:
ERROR("Invalid parameter %u\n", param);
unsigned int param,
unsigned int *value)
{
- int ret;
- unsigned int reg, val;
+ enum pm_ret_status ret;
+ unsigned int ctrlreg, val;
if (param >= PINCTRL_CONFIG_MAX)
return PM_RET_ERROR_NOTSUPPORTED;
switch (param) {
case PINCTRL_CONFIG_SLEW_RATE:
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_SLEWCTRL_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
- if (ret)
+ ret = pm_mmio_read(ctrlreg, &val);
+ if (ret != PM_RET_SUCCESS)
return ret;
*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
break;
case PINCTRL_CONFIG_BIAS_STATUS:
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_PULLSTAT_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(ctrlreg, &val);
if (ret)
return ret;
- if (reg == IOU_SLCR_BANK1_CTRL5)
+ if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF);
*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
break;
case PINCTRL_CONFIG_PULL_CTRL:
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_PULLCTRL_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(ctrlreg, &val);
if (ret)
return ret;
*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
break;
case PINCTRL_CONFIG_SCHMITT_CMOS:
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_SCHCMOS_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(ctrlreg, &val);
if (ret)
return ret;
*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
break;
case PINCTRL_CONFIG_DRIVE_STRENGTH:
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_DRVSTRN0_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(ctrlreg, &val);
if (ret)
return ret;
*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1;
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_DRVSTRN1_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(ctrlreg, &val);
if (ret)
return ret;
*value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
break;
case PINCTRL_CONFIG_VOLTAGE_STATUS:
- reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
+ ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
PINCTRL_VOLTAGE_STAT_REG_OFFSET,
pin);
- ret = pm_mmio_read(reg, &val);
+ ret = pm_mmio_read(ctrlreg, &val);
if (ret)
return ret;
return PM_RET_ERROR_NOTSUPPORTED;
}
- return 0;
+ return PM_RET_SUCCESS;
}
#include "pm_common.h"
-#define FUNCTION_NAME_LEN 16
-#define GROUPS_PAYLOAD_LEN 12
-#define NUM_GROUPS_PER_RESP 6
+#define FUNCTION_NAME_LEN U(16)
+#define GROUPS_PAYLOAD_LEN U(12)
+#define NUM_GROUPS_PER_RESP U(6)
#define END_OF_FUNCTION "END_OF_FUNCTION"
#define END_OF_GROUPS -1
#define PINCTRL_GRP_RESERVED -2
-enum pinctrl_fids {
+//pinctrl function ids
+enum {
PINCTRL_FUNC_CAN0,
PINCTRL_FUNC_CAN1,
PINCTRL_FUNC_ETHERNET0,
PINCTRL_FUNC_TRACE0,
PINCTRL_FUNC_TRACE0_CLK,
PINCTRL_FUNC_TESTSCAN0,
- MAX_FUNCTION,
+ END_FUNCTION,
};
-enum pinctrl_pin {
+#define MAX_FUNCTION (unsigned int)(END_FUNCTION)
+
+// pinctrl pin numbers
+enum {
PINCTRL_PIN_0,
PINCTRL_PIN_1,
PINCTRL_PIN_2,
PINCTRL_PIN_75,
PINCTRL_PIN_76,
PINCTRL_PIN_77,
- MAX_PIN,
+ END_PINS,
};
-enum pinctrl_group_ids {
+#define MAX_PIN (unsigned int)(END_PINS)
+
+// pinctrl group ids
+enum {
PINCTRL_GRP_ETHERNET0_0,
PINCTRL_GRP_ETHERNET1_0,
PINCTRL_GRP_ETHERNET2_0,
PINCTRL_GRP_TESTSCAN0_0,
};
-enum pm_pinctrl_config_param {
+// pinctrl config parameters
+enum {
PINCTRL_CONFIG_SLEW_RATE,
PINCTRL_CONFIG_BIAS_STATUS,
PINCTRL_CONFIG_PULL_CTRL,
PINCTRL_CONFIG_MAX,
};
-enum pm_pinctrl_slew_rate {
- PINCTRL_SLEW_RATE_FAST,
- PINCTRL_SLEW_RATE_SLOW,
-};
+// pinctrl slew rate
+#define PINCTRL_SLEW_RATE_FAST 0U
+#define PINCTRL_SLEW_RATE_SLOW 1U
-enum pm_pinctrl_bias_status {
- PINCTRL_BIAS_DISABLE,
- PINCTRL_BIAS_ENABLE,
-};
+// pinctrl bias status
+#define PINCTRL_BIAS_DISABLE 0U
+#define PINCTRL_BIAS_ENABLE 1U
-enum pm_pinctrl_pull_ctrl {
- PINCTRL_BIAS_PULL_DOWN,
- PINCTRL_BIAS_PULL_UP,
-};
+// pinctrl pull control
+#define PINCTRL_BIAS_PULL_DOWN 0U
+#define PINCTRL_BIAS_PULL_UP 1U
-enum pm_pinctrl_schmitt_cmos {
- PINCTRL_INPUT_TYPE_CMOS,
- PINCTRL_INPUT_TYPE_SCHMITT,
-};
+// pinctrl schmitt cmos type
+#define PINCTRL_INPUT_TYPE_CMOS 0U
+#define PINCTRL_INPUT_TYPE_SCHMITT 1U
-enum pm_pinctrl_drive_strength {
- PINCTRL_DRIVE_STRENGTH_2MA,
- PINCTRL_DRIVE_STRENGTH_4MA,
- PINCTRL_DRIVE_STRENGTH_8MA,
- PINCTRL_DRIVE_STRENGTH_12MA,
-};
+//pinctrl drive strength values
+#define PINCTRL_DRIVE_STRENGTH_2MA 0U
+#define PINCTRL_DRIVE_STRENGTH_4MA 1U
+#define PINCTRL_DRIVE_STRENGTH_8MA 2U
+#define PINCTRL_DRIVE_STRENGTH_12MA 3U
enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
- unsigned int id);
+ unsigned int fid);
enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
unsigned int *id);
enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
enum pm_node_id nid)
{
- return pm_api_pinctrl_set_function(pin, nid);
+ return pm_api_pinctrl_set_function(pin, (unsigned int)nid);
}
/**
break;
case PM_QID_CLOCK_GET_TOPOLOGY:
ret = pm_clock_get_topology(arg1, arg2, &data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
ret = pm_clock_get_fixedfactor_params(arg1, &data[1], &data[2]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_CLOCK_GET_PARENTS:
ret = pm_clock_get_parents(arg1, arg2, &data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_CLOCK_GET_ATTRIBUTES:
ret = pm_clock_get_attributes(arg1, &data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_PINCTRL_GET_NUM_PINS:
ret = pm_pinctrl_get_num_pins(&data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
ret = pm_pinctrl_get_num_functions(&data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
ret = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_PINCTRL_GET_FUNCTION_NAME:
ret = pm_pinctrl_get_function_name(arg1, (char *)data);
case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
ret = pm_pinctrl_get_function_groups(arg1, arg2,
(uint16_t *)&data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
case PM_QID_PINCTRL_GET_PIN_GROUPS:
ret = pm_pinctrl_get_pin_groups(arg1, arg2,
(uint16_t *)&data[1]);
- data[0] = ret;
+ data[0] = (unsigned int)ret;
break;
default:
ret = PM_RET_ERROR_ARGS;
WARN("Unimplemented query service call: 0x%x\n", qid);
+ break;
}
return ret;
enum pm_ret_status pm_pinctrl_request(unsigned int pin);
enum pm_ret_status pm_pinctrl_release(unsigned int pin);
enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
- unsigned int *value);
+ enum pm_node_id *nid);
enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
- unsigned int value);
+ enum pm_node_id nid);
enum pm_ret_status pm_pinctrl_get_config(unsigned int pin,
unsigned int param,
unsigned int *value);
case PM_PINCTRL_GET_FUNCTION:
{
- uint32_t value;
+ uint32_t value = 0;
ret = pm_pinctrl_get_function(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
case PM_QUERY_DATA:
{
- uint32_t data[4];
+ uint32_t data[4] = { 0 };
ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], data);
uint64_t value;
ret = pm_clock_getrate(pm_arg[0], &value);
- SMC_RET2(handle, (uint64_t)ret | (value & 0xFFFFFFFF) << 32,
- (value >> 32) & 0xFFFFFFFF);
+ SMC_RET2(handle, (uint64_t)ret |
+ (((uint64_t)value & 0xFFFFFFFFU) << 32U),
+ (value >> 32U) & 0xFFFFFFFFU);
}
* ZYNQMP memory map related constants
******************************************************************************/
/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE 0xFF000000
-#define DEVICE0_SIZE 0x00E00000
-#define DEVICE1_BASE 0xF9000000
-#define DEVICE1_SIZE 0x00800000
+#define DEVICE0_BASE U(0xFF000000)
+#define DEVICE0_SIZE U(0x00E00000)
+#define DEVICE1_BASE U(0xF9000000)
+#define DEVICE1_SIZE U(0x00800000)
/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
-#define CRF_APB_BASE 0xFD1A0000
-#define CRF_APB_SIZE 0x00600000
-#define CRF_APB_CLK_BASE 0xFD1A0020
+#define CRF_APB_BASE U(0xFD1A0000)
+#define CRF_APB_SIZE U(0x00600000)
+#define CRF_APB_CLK_BASE U(0xFD1A0020)
/* CRF registers and bitfields */
#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
-#define CRF_APB_RST_FPD_APU_ACPU_RESET (1 << 0)
-#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (1 << 10)
+#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
+#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
/* CRL registers and bitfields */
-#define CRL_APB_BASE 0xFF5E0000
+#define CRL_APB_BASE U(0xFF5E0000)
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
-#define CRL_APB_CLK_BASE 0xFF5E0020
+#define CRL_APB_CLK_BASE U(0xFF5E0020)
-#define CRL_APB_RPU_AMBA_RESET (1 << 2)
-#define CRL_APB_RPLL_CTRL_BYPASS (1 << 3)
+#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
+#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
-#define CRL_APB_RESET_CTRL_SOFT_RESET (1 << 4)
+#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
-#define CRL_APB_BOOT_MODE_MASK (0xf << 0)
-#define ZYNQMP_BOOTMODE_JTAG 0
+#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
+#define ZYNQMP_BOOTMODE_JTAG U(0)
/* system counter registers and bitfields */
#define IOU_SCNTRS_BASE 0xFF260000
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
-#define IOU_SLCR_BASEADDR 0xFF180000
+#define IOU_SLCR_BASEADDR U(0xFF180000)
-#define ZYNQMP_RPU_GLBL_CNTL 0xFF9A0000
-#define ZYNQMP_RPU0_CFG 0xFF9A0100
-#define ZYNQMP_RPU1_CFG 0xFF9A0200
-#define ZYNQMP_SLSPLIT_MASK 0x08
-#define ZYNQMP_TCM_COMB_MASK 0x40
-#define ZYNQMP_SLCLAMP_MASK 0x10
-#define ZYNQMP_VINITHI_MASK 0x04
+#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
+#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
+#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
+#define ZYNQMP_SLSPLIT_MASK U(0x08)
+#define ZYNQMP_TCM_COMB_MASK U(0x40)
+#define ZYNQMP_SLCLAMP_MASK U(0x10)
+#define ZYNQMP_VINITHI_MASK U(0x04)
/* Tap delay bypass */
-#define IOU_TAPDLY_BYPASS 0XFF180390
-#define TAP_DELAY_MASK 0x7
+#define IOU_TAPDLY_BYPASS U(0XFF180390)
+#define TAP_DELAY_MASK U(0x7)
/* SGMII mode */
-#define IOU_GEM_CTRL 0xFF180360
-#define IOU_GEM_CLK_CTRL 0xFF180308
-#define SGMII_SD_MASK 0x3
-#define SGMII_SD_OFFSET 2
-#define SGMII_PCS_SD_0 0x0
-#define SGMII_PCS_SD_1 0x1
-#define SGMII_PCS_SD_PHY 0x2
-#define GEM_SGMII_MASK 0x4
-#define GEM_CLK_CTRL_MASK 0xF
-#define GEM_CLK_CTRL_OFFSET 5
-#define GEM_RX_SRC_SEL_GTR 0x1
-#define GEM_SGMII_MODE 0x4
+#define IOU_GEM_CTRL U(0xFF180360)
+#define IOU_GEM_CLK_CTRL U(0xFF180308)
+#define SGMII_SD_MASK U(0x3)
+#define SGMII_SD_OFFSET U(2)
+#define SGMII_PCS_SD_0 U(0x0)
+#define SGMII_PCS_SD_1 U(0x1)
+#define SGMII_PCS_SD_PHY U(0x2)
+#define GEM_SGMII_MASK U(0x4)
+#define GEM_CLK_CTRL_MASK U(0xF)
+#define GEM_CLK_CTRL_OFFSET U(5)
+#define GEM_RX_SRC_SEL_GTR U(0x1)
+#define GEM_SGMII_MODE U(0x4)
/* SD DLL reset */
-#define ZYNQMP_SD_DLL_CTRL 0xFF180358
-#define ZYNQMP_SD0_DLL_RST_MASK 0x00000004
-#define ZYNQMP_SD0_DLL_RST 0x00000004
-#define ZYNQMP_SD1_DLL_RST_MASK 0x00040000
-#define ZYNQMP_SD1_DLL_RST 0x00040000
+#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
+#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
+#define ZYNQMP_SD0_DLL_RST U(0x00000004)
+#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
+#define ZYNQMP_SD1_DLL_RST U(0x00040000)
/* SD tap delay */
-#define ZYNQMP_SD_DLL_CTRL 0xFF180358
-#define ZYNQMP_SD_ITAP_DLY 0xFF180314
-#define ZYNQMP_SD_OTAP_DLY 0xFF180318
-#define ZYNQMP_SD_TAP_OFFSET 16
-#define ZYNQMP_SD_ITAPCHGWIN_MASK 0x200
-#define ZYNQMP_SD_ITAPCHGWIN 0x200
-#define ZYNQMP_SD_ITAPDLYENA_MASK 0x100
-#define ZYNQMP_SD_ITAPDLYENA 0x100
-#define ZYNQMP_SD_ITAPDLYSEL_MASK 0xFF
-#define ZYNQMP_SD_OTAPDLYSEL_MASK 0x3F
-#define ZYNQMP_SD_OTAPDLYENA_MASK 0x40
-#define ZYNQMP_SD_OTAPDLYENA 0x40
+#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
+#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
+#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
+#define ZYNQMP_SD_TAP_OFFSET U(16)
+#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
+#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
+#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
+#define ZYNQMP_SD_ITAPDLYENA U(0x100)
+#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
+#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
+#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
+#define ZYNQMP_SD_OTAPDLYENA U(0x40)
/* Clock control registers */
/* Full power domain clocks */
/* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U)
-#define GGS_NUM_REGS (4)
+#define GGS_NUM_REGS U(4)
/* Persistent global general storage register base address */
#define PGGS_BASEADDR (0xFFD80050U)
-#define PGGS_NUM_REGS (4)
+#define PGGS_NUM_REGS U(4)
#endif /* __ZYNQMP_DEF_H__ */
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