mediatek: fixes for Ethernet on MT7988 SoC

 * fix switch ports with modes other than 1000M/Full
 * set 32-bit dma_coherent_mask to get PPE to work with 4 GiB of RAM
 * sync driver for built-in 1GE PHY with MediaTek SDK sources

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 4ae2f43b3a24e8a74963852f9d2fb8fee0872f31)

diff --git a/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
new file mode 100644 (file)
index 0000000..29dca26
--- /dev/null
+++ b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
@@ -0,0 +1,46 @@
+From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
+Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 03:19:49 +0000
+Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
+ working
+To: Felix Fietkau <nbd@nbd.name>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Mark Lee <Mark-MC.Lee@mediatek.com>,
+    Lorenzo Bianconi <lorenzo@kernel.org>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Set DMA coherent mask to 32-bit which makes PPE offloading engine start
+working on BPi-R4 which got 4 GiB of RAM.
+
+Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
+Suggested-by: Elad Yifee <eladwf@users.github.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4830,7 +4830,10 @@ static int mtk_probe(struct platform_dev
+       }
+ 
+       if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
+-              err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
++              err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
++              if (!err)
++                      err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++
+               if (err) {
+                       dev_err(&pdev->dev, "Wrong DMA config\n");
+                       return -EINVAL;

diff --git a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
new file mode 100644 (file)
index 0000000..f2e91d3
--- /dev/null
+++ b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -0,0 +1,45 @@
+From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
+Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 04:17:11 +0000
+Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
+To: Arınç ÜNAL <arinc.unal@arinc9.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    DENG Qingfang <dqfext@gmail.com>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Florian Fainelli <f.fainelli@gmail.com>,
+    Vladimir Oltean <olteanv@gmail.com>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Setup PMCR port register for actual speed and duplex on internally
+connected PHYs of the MT7988 built-in switch. This fixes links with
+speeds other than 1000M.
+
+Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2832,8 +2832,7 @@ static void mt753x_phylink_mac_link_up(s
+       /* MT753x MAC works in 1G full duplex mode for all up-clocked
+        * variants.
+        */
+-      if (interface == PHY_INTERFACE_MODE_INTERNAL ||
+-          interface == PHY_INTERFACE_MODE_TRGMII ||
++      if (interface == PHY_INTERFACE_MODE_TRGMII ||
+           (phy_interface_mode_is_8023z(interface))) {
+               speed = SPEED_1000;
+               duplex = DUPLEX_FULL;

diff --git a/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
new file mode 100644 (file)
index 0000000..f983be4
--- /dev/null
+++ b/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
@@ -0,0 +1,270 @@
+From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
+Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 02:27:04 +0000
+Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
+To: Daniel Golle <daniel@makrotopia.org>,
+    Qingfang Deng <dqfext@gmail.com>,
+    SkyLake Huang <SkyLake.Huang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Heiner Kallweit <hkallweit1@gmail.com>,
+    Russell King <linux@armlinux.org.uk>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Sync initialization and calibration routines with MediaTek's reference
+driver. Improves compliance and resolves link stability issues with
+CH340 IoT devices connected to MT798x built-in PHYs.
+
+Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
+ 1 file changed, 81 insertions(+), 66 deletions(-)
+
+--- a/drivers/net/phy/mediatek-ge-soc.c
++++ b/drivers/net/phy/mediatek-ge-soc.c
+@@ -479,7 +479,7 @@ static int tx_r50_fill_result(struct phy
+       u16 reg, val;
+ 
+       if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
+-              bias = -2;
++              bias = -1;
+ 
+       val = clamp_val(bias + tx_r50_cal_val, 0, 63);
+ 
+@@ -695,6 +695,11 @@ restore:
+ static void mt798x_phy_common_finetune(struct phy_device *phydev)
+ {
+       phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++      /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
++      __phy_write(phydev, 0x11, 0xc71);
++      __phy_write(phydev, 0x12, 0xc);
++      __phy_write(phydev, 0x10, 0x8fae);
++
+       /* EnabRandUpdTrig = 1 */
+       __phy_write(phydev, 0x11, 0x2f00);
+       __phy_write(phydev, 0x12, 0xe);
+@@ -705,15 +710,56 @@ static void mt798x_phy_common_finetune(s
+       __phy_write(phydev, 0x12, 0x0);
+       __phy_write(phydev, 0x10, 0x83aa);
+ 
+-      /* TrFreeze = 0 */
++      /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
++      __phy_write(phydev, 0x11, 0x240);
++      __phy_write(phydev, 0x12, 0x0);
++      __phy_write(phydev, 0x10, 0x9680);
++
++      /* TrFreeze = 0 (mt7988 default) */
+       __phy_write(phydev, 0x11, 0x0);
+       __phy_write(phydev, 0x12, 0x0);
+       __phy_write(phydev, 0x10, 0x9686);
+ 
++      /* SSTrKp100 = 5 */
++      /* SSTrKf100 = 6 */
++      /* SSTrKp1000Mas = 5 */
++      /* SSTrKf1000Mas = 6 */
+       /* SSTrKp1000Slv = 5 */
++      /* SSTrKf1000Slv = 6 */
+       __phy_write(phydev, 0x11, 0xbaef);
+       __phy_write(phydev, 0x12, 0x2e);
+       __phy_write(phydev, 0x10, 0x968c);
++      phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++}
++
++static void mt7981_phy_finetune(struct phy_device *phydev)
++{
++      u16 val[8] = { 0x01ce, 0x01c1,
++                     0x020f, 0x0202,
++                     0x03d0, 0x03c0,
++                     0x0013, 0x0005 };
++      int i, k;
++
++      /* 100M eye finetune:
++       * Keep middle level of TX MLT3 shapper as default.
++       * Only change TX MLT3 overshoot level here.
++       */
++      for (k = 0, i = 1; i < 12; i++) {
++              if (i % 3 == 0)
++                      continue;
++              phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
++      }
++
++      phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++      /* ResetSyncOffset = 6 */
++      __phy_write(phydev, 0x11, 0x600);
++      __phy_write(phydev, 0x12, 0x0);
++      __phy_write(phydev, 0x10, 0x8fc0);
++
++      /* VgaDecRate = 1 */
++      __phy_write(phydev, 0x11, 0x4c2a);
++      __phy_write(phydev, 0x12, 0x3e);
++      __phy_write(phydev, 0x10, 0x8fa4);
+ 
+       /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
+        * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
+@@ -728,7 +774,7 @@ static void mt798x_phy_common_finetune(s
+       __phy_write(phydev, 0x10, 0x8ec0);
+       phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ 
+-      /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
++      /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
+       phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+                      MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+                      BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
+@@ -761,48 +807,6 @@ static void mt798x_phy_common_finetune(s
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
+ }
+ 
+-static void mt7981_phy_finetune(struct phy_device *phydev)
+-{
+-      u16 val[8] = { 0x01ce, 0x01c1,
+-                     0x020f, 0x0202,
+-                     0x03d0, 0x03c0,
+-                     0x0013, 0x0005 };
+-      int i, k;
+-
+-      /* 100M eye finetune:
+-       * Keep middle level of TX MLT3 shapper as default.
+-       * Only change TX MLT3 overshoot level here.
+-       */
+-      for (k = 0, i = 1; i < 12; i++) {
+-              if (i % 3 == 0)
+-                      continue;
+-              phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
+-      }
+-
+-      phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+-      /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+-      __phy_write(phydev, 0x11, 0xc71);
+-      __phy_write(phydev, 0x12, 0xc);
+-      __phy_write(phydev, 0x10, 0x8fae);
+-
+-      /* ResetSyncOffset = 6 */
+-      __phy_write(phydev, 0x11, 0x600);
+-      __phy_write(phydev, 0x12, 0x0);
+-      __phy_write(phydev, 0x10, 0x8fc0);
+-
+-      /* VgaDecRate = 1 */
+-      __phy_write(phydev, 0x11, 0x4c2a);
+-      __phy_write(phydev, 0x12, 0x3e);
+-      __phy_write(phydev, 0x10, 0x8fa4);
+-
+-      /* FfeUpdGainForce = 4 */
+-      __phy_write(phydev, 0x11, 0x240);
+-      __phy_write(phydev, 0x12, 0x0);
+-      __phy_write(phydev, 0x10, 0x9680);
+-
+-      phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+-}
+-
+ static void mt7988_phy_finetune(struct phy_device *phydev)
+ {
+       u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
+@@ -817,17 +821,7 @@ static void mt7988_phy_finetune(struct p
+       /* TCT finetune */
+       phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
+ 
+-      /* Disable TX power saving */
+-      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+-                     MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+-
+       phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+-
+-      /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
+-      __phy_write(phydev, 0x11, 0x671);
+-      __phy_write(phydev, 0x12, 0xc);
+-      __phy_write(phydev, 0x10, 0x8fae);
+-
+       /* ResetSyncOffset = 5 */
+       __phy_write(phydev, 0x11, 0x500);
+       __phy_write(phydev, 0x12, 0x0);
+@@ -835,13 +829,27 @@ static void mt7988_phy_finetune(struct p
+ 
+       /* VgaDecRate is 1 at default on mt7988 */
+ 
+-      phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++      /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
++       * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
++       */
++      __phy_write(phydev, 0x11, 0xb90a);
++      __phy_write(phydev, 0x12, 0x6f);
++      __phy_write(phydev, 0x10, 0x8f82);
++
++      /* RemAckCntLimitCtrl = 1 */
++      __phy_write(phydev, 0x11, 0xfbba);
++      __phy_write(phydev, 0x12, 0xc3);
++      __phy_write(phydev, 0x10, 0x87f8);
+ 
+-      phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
+-      /* TxClkOffset = 2 */
+-      __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
+-                   FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
+       phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++      /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
++      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
++                     MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++                     BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
++
++      /* rg_tr_lpf_cnt_val = 1023 */
++      phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
+ }
+ 
+ static void mt798x_phy_eee(struct phy_device *phydev)
+@@ -874,11 +882,11 @@ static void mt798x_phy_eee(struct phy_de
+                      MTK_PHY_LPI_SLV_SEND_TX_EN,
+                      FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
+ 
+-      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
+-                     MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
+-                     MTK_PHY_LPI_TXPCS_LOC_RCV,
+-                     FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
++      /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
++      phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
++                         MTK_PHY_LPI_TXPCS_LOC_RCV);
+ 
++      /* This also fixes some IoT issues, such as CH340 */
+       phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
+                      MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
+                      FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
+@@ -912,7 +920,7 @@ static void mt798x_phy_eee(struct phy_de
+       __phy_write(phydev, 0x12, 0x0);
+       __phy_write(phydev, 0x10, 0x9690);
+ 
+-      /* REG_EEE_st2TrKf1000 = 3 */
++      /* REG_EEE_st2TrKf1000 = 2 */
+       __phy_write(phydev, 0x11, 0x114f);
+       __phy_write(phydev, 0x12, 0x2);
+       __phy_write(phydev, 0x10, 0x969a);
+@@ -937,7 +945,7 @@ static void mt798x_phy_eee(struct phy_de
+       __phy_write(phydev, 0x12, 0x0);
+       __phy_write(phydev, 0x10, 0x96b8);
+ 
+-      /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
++      /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
+       __phy_write(phydev, 0x11, 0x1463);
+       __phy_write(phydev, 0x12, 0x0);
+       __phy_write(phydev, 0x10, 0x96ca);
+@@ -1198,6 +1206,13 @@ static int mt7988_phy_probe(struct phy_d
+ 
+       mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
+ 
++      /* Disable TX power saving at probing to:
++       * 1. Meet common mode compliance test criteria
++       * 2. Make sure that TX-VCM calibration works fine
++       */
++      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
++                     MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
++
+       return mt798x_phy_calibration(phydev);
+ }
+ 

diff --git a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
index 7b78033ffb77914638edd740e8f7b6b2ebc6732c..af95dcf8d299af24f7f1da6cdded67f6a3189879 100644 (file)
--- a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ b/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
@@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
        mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
        if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5163,11 +5163,15 @@ static const struct mtk_soc_data mt2701_
+@@ -5166,11 +5166,15 @@ static const struct mtk_soc_data mt2701_
        .required_clks = MT7623_CLKS_BITMAP,
        .required_pctl = true,
        .version = 1,
@@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN,
                .dma_len_offset = 16,
        },
-@@ -5183,11 +5187,15 @@ static const struct mtk_soc_data mt7621_
+@@ -5186,11 +5190,15 @@ static const struct mtk_soc_data mt7621_
        .offload_version = 1,
        .hash_offset = 2,
        .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN,
                .dma_len_offset = 16,
        },
-@@ -5205,11 +5213,15 @@ static const struct mtk_soc_data mt7622_
+@@ -5208,11 +5216,15 @@ static const struct mtk_soc_data mt7622_
        .hash_offset = 2,
        .has_accounting = true,
        .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN,
                .dma_len_offset = 16,
        },
-@@ -5226,11 +5238,15 @@ static const struct mtk_soc_data mt7623_
+@@ -5229,11 +5241,15 @@ static const struct mtk_soc_data mt7623_
        .hash_offset = 2,
        .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
        .disable_pll_modes = true,
@@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN,
                .dma_len_offset = 16,
        },
-@@ -5245,11 +5261,15 @@ static const struct mtk_soc_data mt7629_
+@@ -5248,11 +5264,15 @@ static const struct mtk_soc_data mt7629_
        .required_pctl = false,
        .has_accounting = true,
        .version = 1,
@@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN,
                .dma_len_offset = 16,
        },
-@@ -5267,11 +5287,15 @@ static const struct mtk_soc_data mt7981_
+@@ -5270,11 +5290,15 @@ static const struct mtk_soc_data mt7981_
        .hash_offset = 4,
        .has_accounting = true,
        .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
                .dma_len_offset = 8,
        },
-@@ -5289,11 +5313,15 @@ static const struct mtk_soc_data mt7986_
+@@ -5292,11 +5316,15 @@ static const struct mtk_soc_data mt7986_
        .hash_offset = 4,
        .has_accounting = true,
        .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
                .dma_len_offset = 8,
        },
-@@ -5311,11 +5339,15 @@ static const struct mtk_soc_data mt7988_
+@@ -5314,11 +5342,15 @@ static const struct mtk_soc_data mt7988_
        .hash_offset = 4,
        .has_accounting = true,
        .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
@@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
                .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
                .dma_len_offset = 8,
        },
-@@ -5328,11 +5360,15 @@ static const struct mtk_soc_data rt5350_
+@@ -5331,11 +5363,15 @@ static const struct mtk_soc_data rt5350_
        .required_clks = MT7628_CLKS_BITMAP,
        .required_pctl = false,
        .version = 1,

diff --git a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
index df8e988eb5a76c5079794e07365699e91b7965c3..ea94bb5e05642f58c3450d33ccb385df451c99e4 100644 (file)
--- a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ b/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
@@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
                /* Set FE to PDMAv2 if necessary */
                val = mtk_r32(eth, MTK_FE_GLO_MISC);
                mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5293,11 +5293,11 @@ static const struct mtk_soc_data mt7981_
+@@ -5296,11 +5296,11 @@ static const struct mtk_soc_data mt7981_
                .dma_len_offset = 8,
        },
        .rx = {
@@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
        },
  };
  
-@@ -5319,11 +5319,11 @@ static const struct mtk_soc_data mt7986_
+@@ -5322,11 +5322,11 @@ static const struct mtk_soc_data mt7986_
                .dma_len_offset = 8,
        },
        .rx = {