drm/amdgpu: use new scheduler load balancing for VMs
authorChristian König <christian.koenig@amd.com>
Thu, 12 Jul 2018 13:15:21 +0000 (15:15 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Aug 2018 16:10:45 +0000 (11:10 -0500)
Instead of the fixed round robin use let the scheduler balance the load
of page table updates.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/si_dma.c

index 9c594763ddff843be3c716844fdcd3c7cec9eaf6..0b4815c1e181a786ac5d9c7f98545ab775e53023 100644 (file)
@@ -2348,7 +2348,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        adev->mman.buffer_funcs = NULL;
        adev->mman.buffer_funcs_ring = NULL;
        adev->vm_manager.vm_pte_funcs = NULL;
-       adev->vm_manager.vm_pte_num_rings = 0;
+       adev->vm_manager.vm_pte_num_rqs = 0;
        adev->gmc.gmc_funcs = NULL;
        adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
        bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
index e40ca86764182567d4a24f3a76e70b2793eb993a..995ad5e83611b99706345f7b062d7a4431dfffb6 100644 (file)
@@ -2569,9 +2569,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
        struct amdgpu_bo *root;
        const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
                AMDGPU_VM_PTE_COUNT(adev) * 8);
-       unsigned ring_instance;
-       struct amdgpu_ring *ring;
-       struct drm_sched_rq *rq;
        unsigned long size;
        uint64_t flags;
        int r, i;
@@ -2587,12 +2584,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
        INIT_LIST_HEAD(&vm->freed);
 
        /* create scheduler entity for page table updates */
-
-       ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
-       ring_instance %= adev->vm_manager.vm_pte_num_rings;
-       ring = adev->vm_manager.vm_pte_rings[ring_instance];
-       rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-       r = drm_sched_entity_init(&vm->entity, &rq, 1, NULL);
+       r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
+                                 adev->vm_manager.vm_pte_num_rqs, NULL);
        if (r)
                return r;
 
@@ -2901,7 +2894,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
        for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
                adev->vm_manager.seqno[i] = 0;
 
-       atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
        spin_lock_init(&adev->vm_manager.prt_lock);
        atomic_set(&adev->vm_manager.num_prt_users, 0);
 
index ffda53420f8c1a68e1478054393562a457ee6ae0..1162c2bf3138e04e33bddcb28303d38194974fb3 100644 (file)
@@ -265,10 +265,9 @@ struct amdgpu_vm_manager {
        /* vram base address for page table entry  */
        u64                                     vram_base_offset;
        /* vm pte handling */
-       const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
-       struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
-       unsigned                                vm_pte_num_rings;
-       atomic_t                                vm_pte_next_ring;
+       const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
+       struct drm_sched_rq                     *vm_pte_rqs[AMDGPU_MAX_RINGS];
+       unsigned                                vm_pte_num_rqs;
 
        /* partial resident texture handling */
        spinlock_t                              prt_lock;
index d0fa2aac238884630eba999d325b2e7d9e384504..154b1499b07ec47e8964602907b20e4d3f42d71c 100644 (file)
@@ -1386,15 +1386,17 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
 
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
+       struct drm_gpu_scheduler *sched;
        unsigned i;
 
        if (adev->vm_manager.vm_pte_funcs == NULL) {
                adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
-               for (i = 0; i < adev->sdma.num_instances; i++)
-                       adev->vm_manager.vm_pte_rings[i] =
-                               &adev->sdma.instance[i].ring;
-
-               adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       sched = &adev->sdma.instance[i].ring.sched;
+                       adev->vm_manager.vm_pte_rqs[i] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
        }
 }
 
index 15ae4bc9c072741d6b8fb319b9371b87e08ac6c4..c403bdf8ad708bac558a60dc7b7f6f521c4d27ae 100644 (file)
@@ -1312,15 +1312,17 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
 
 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
+       struct drm_gpu_scheduler *sched;
        unsigned i;
 
        if (adev->vm_manager.vm_pte_funcs == NULL) {
                adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
-               for (i = 0; i < adev->sdma.num_instances; i++)
-                       adev->vm_manager.vm_pte_rings[i] =
-                               &adev->sdma.instance[i].ring;
-
-               adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       sched = &adev->sdma.instance[i].ring.sched;
+                       adev->vm_manager.vm_pte_rqs[i] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
        }
 }
 
index 1e07ff274d73433b34e14a9aa4b94caf04bba961..2677d6a1bf42147c999f8fc1348fe512993cae87 100644 (file)
@@ -1752,15 +1752,17 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
 
 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
+       struct drm_gpu_scheduler *sched;
        unsigned i;
 
        if (adev->vm_manager.vm_pte_funcs == NULL) {
                adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
-               for (i = 0; i < adev->sdma.num_instances; i++)
-                       adev->vm_manager.vm_pte_rings[i] =
-                               &adev->sdma.instance[i].ring;
-
-               adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       sched = &adev->sdma.instance[i].ring.sched;
+                       adev->vm_manager.vm_pte_rqs[i] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
        }
 }
 
index 407ed8a271b7627eba9a6261b0b6a4051a2a8b65..df138401fbf8fcaac56e50b38300a7f5edb59b11 100644 (file)
@@ -1796,15 +1796,17 @@ static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
 
 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
+       struct drm_gpu_scheduler *sched;
        unsigned i;
 
        if (adev->vm_manager.vm_pte_funcs == NULL) {
                adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
-               for (i = 0; i < adev->sdma.num_instances; i++)
-                       adev->vm_manager.vm_pte_rings[i] =
-                               &adev->sdma.instance[i].ring;
-
-               adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       sched = &adev->sdma.instance[i].ring.sched;
+                       adev->vm_manager.vm_pte_rqs[i] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
        }
 }
 
index b75d901ba3c45186c7e941b58b4919316157d89c..fafaf259b17b837b4dbd27ab9103b93bdfe919a5 100644 (file)
@@ -879,15 +879,17 @@ static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
 
 static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
+       struct drm_gpu_scheduler *sched;
        unsigned i;
 
        if (adev->vm_manager.vm_pte_funcs == NULL) {
                adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
-               for (i = 0; i < adev->sdma.num_instances; i++)
-                       adev->vm_manager.vm_pte_rings[i] =
-                               &adev->sdma.instance[i].ring;
-
-               adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       sched = &adev->sdma.instance[i].ring.sched;
+                       adev->vm_manager.vm_pte_rqs[i] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
        }
 }