powerpc/perf: Remove l2 bus events from HW cache event array

Remove PM_L2_ST_MISS and PM_L2_ST from HW cache event array since
these are bus events. And these needs to be programmed in groups.
Hence remove them.

Fixes: f1fb60bfde65 ('powerpc/perf: Export Power9 generic and cache events to sysfs')
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index deffe1c3c51816123793dad7e5a1a023c7d1893a..0ff9c43733e97179bacbe9ca406e834c37e9cc7a 100644 (file)
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -171,8 +171,6 @@ CACHE_EVENT_ATTR(L1-icache-prefetches,              PM_IC_PREF_WRITE);
 CACHE_EVENT_ATTR(LLC-load-misses,              PM_DATA_FROM_L3MISS);
 CACHE_EVENT_ATTR(LLC-loads,                    PM_DATA_FROM_L3);
 CACHE_EVENT_ATTR(LLC-prefetches,               PM_L3_PREF_ALL);
-CACHE_EVENT_ATTR(LLC-store-misses,             PM_L2_ST_MISS);
-CACHE_EVENT_ATTR(LLC-stores,                   PM_L2_ST);
 CACHE_EVENT_ATTR(branch-load-misses,           PM_BR_MPRED_CMPL);
 CACHE_EVENT_ATTR(branch-loads,                 PM_BR_CMPL);
 CACHE_EVENT_ATTR(dTLB-load-misses,             PM_DTLB_MISS);
@@ -197,8 +195,6 @@ static struct attribute *power9_events_attr[] = {
        CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
        CACHE_EVENT_PTR(PM_DATA_FROM_L3),
        CACHE_EVENT_PTR(PM_L3_PREF_ALL),
-       CACHE_EVENT_PTR(PM_L2_ST_MISS),
-       CACHE_EVENT_PTR(PM_L2_ST),
        CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
        CACHE_EVENT_PTR(PM_BR_CMPL),
        CACHE_EVENT_PTR(PM_DTLB_MISS),
@@ -346,8 +342,8 @@ static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                        [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
                },
                [ C(OP_WRITE) ] = {
-                       [ C(RESULT_ACCESS) ] = PM_L2_ST,
-                       [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
+                       [ C(RESULT_ACCESS) ] = 0,
+                       [ C(RESULT_MISS)   ] = 0,
                },
                [ C(OP_PREFETCH) ] = {
                        [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,