CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_LPFC is not set
CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_USB_AIPTEK is not set
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_APPLETOUCH is not set
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_RNDIS_HOST=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
CONFIG_USB_NET_ZAURUS=m
# CONFIG_USB_OHCI_BIG_ENDIAN is not set
# CONFIG_USB_OHCI_HCD is not set
--- /dev/null
+--- linux-2.6.24.5/drivers/rtc/rtc-ds1672.c 2008-04-19 03:53:39.000000000 +0200
++++ linux-2.6.24.5-owrt/drivers/rtc/rtc-ds1672.c 2008-04-29 22:16:41.000000000 +0200
+@@ -13,10 +13,10 @@
+ #include <linux/i2c.h>
+ #include <linux/rtc.h>
+
+-#define DRV_VERSION "0.3"
++#define DRV_VERSION "0.4"
+
+-/* Addresses to scan: none. This chip cannot be detected. */
+-static const unsigned short normal_i2c[] = { I2C_CLIENT_END };
++/* Addresses to scan: 0x68 */
++static const unsigned short normal_i2c[] = { 0x68, I2C_CLIENT_END };
+
+ /* Insmod parameters */
+ I2C_CLIENT_INSMOD;
FEATURES:=squashfs
SUBTARGETS=generic harddisk
-LINUX_VERSION:=2.6.24.5
+LINUX_VERSION:=2.6.25
include $(INCLUDE_DIR)/target.mk
diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c
--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 14:11:10.000000000 +0100
+++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 14:09:30.000000000 +0100
-@@ -90,9 +90,36 @@
+@@ -90,9 +90,37 @@
.resource = ap1000_uart_resources
};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ap1000_plat_eth[] = {
+ {
-+ .phy = 4,
++ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
++ .phy_mask = 0x1e,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
--- /dev/null
+diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/Kconfig linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.24.5/arch/arm/mach-ixp4xx/Kconfig 2008-04-28 20:22:27.000000000 +0200
++++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Kconfig 2008-04-28 20:26:44.000000000 +0200
+@@ -25,6 +25,14 @@
+ Avila Network Platform. For more information on this platform,
+ see <file:Documentation/arm/IXP4xx>.
+
++config MACH_CAMBRIA
++ bool "Cambria"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the Gateworks
++ Cambria series. For more information on this platform,
++ see <file:Documentation/arm/IXP4xx>.
++
+ config MACH_LOFT
+ bool "Loft"
+ depends on MACH_AVILA
+@@ -200,7 +208,7 @@
+
+ config CPU_IXP43X
+ bool
+- depends on MACH_KIXRP435
++ depends on MACH_KIXRP435 || MACH_CAMBRIA
+ default y
+
+ config MACH_GTWX5715
+diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/Makefile linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.24.5/arch/arm/mach-ixp4xx/Makefile 2008-04-28 20:22:27.000000000 +0200
++++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Makefile 2008-04-28 20:26:44.000000000 +0200
+@@ -7,6 +7,7 @@
+
+ obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
++obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
+ obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
+ obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
+ obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
+@@ -28,6 +29,7 @@
+
+ obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
+ obj-$(CONFIG_MACH_AVILA) += avila-setup.o
++obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
+ obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
+ obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
+ obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
+diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-pci.c linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-pci.c
+--- linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-pci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-pci.c 2008-04-28 20:30:35.000000000 +0200
+@@ -0,0 +1,74 @@
++/*
++ * arch/arch/mach-ixp4xx/cambria-pci.c
++ *
++ * PCI setup routines for Gateworks Cambria series
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init cambria_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO11;
++ else if (slot == 2)
++ return IRQ_IXP4XX_GPIO10;
++ else if (slot == 3)
++ return IRQ_IXP4XX_GPIO9;
++ else if (slot == 4)
++ return IRQ_IXP4XX_GPIO8;
++ else return -1;
++}
++
++struct hw_pci cambria_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = cambria_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = cambria_map_irq,
++};
++
++int __init cambria_pci_init(void)
++{
++ if (machine_is_cambria())
++ pci_common_init(&cambria_pci);
++ return 0;
++}
++
++subsys_initcall(cambria_pci_init);
+diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-setup.c linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-setup.c
+--- linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-setup.c 2008-04-28 21:07:16.000000000 +0200
+@@ -0,0 +1,250 @@
++/*
++ * arch/arm/mach-ixp4xx/cambria-setup.c
++ *
++ * Board setup for the Gateworks Cambria series
++ *
++ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/if_ether.h>
++#include <linux/socket.h>
++#include <linux/netdevice.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++#ifdef CONFIG_SENSORS_EEPROM
++# include <linux/i2c.h>
++# include <linux/eeprom.h>
++#endif
++
++#include <linux/i2c-gpio.h>
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data cambria_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource cambria_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device cambria_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &cambria_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &cambria_flash_resource,
++};
++
++static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
++ .sda_pin = 7,
++ .scl_pin = 6,
++};
++
++static struct platform_device cambria_i2c_gpio = {
++ .name = "i2c-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = &cambria_i2c_gpio_data,
++ },
++};
++
++static struct resource cambria_uart_resource = {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port cambria_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device cambria_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = cambria_uart_data,
++ },
++ .num_resources = 1,
++ .resource = &cambria_uart_resource,
++};
++
++static struct resource cambria_pata_resources[] = {
++ {
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "intrq",
++ .start = IRQ_IXP4XX_GPIO12,
++ .end = IRQ_IXP4XX_GPIO12,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct ixp4xx_pata_data cambria_pata_data = {
++ .cs0_bits = 0xbfff3c03,
++ .cs1_bits = 0xbfff3c03,
++};
++
++static struct platform_device cambria_pata = {
++ .name = "pata_ixp4xx_cf",
++ .id = 0,
++ .dev.platform_data = &cambria_pata_data,
++ .num_resources = ARRAY_SIZE(cambria_pata_resources),
++ .resource = cambria_pata_resources,
++};
++
++static struct eth_plat_info cambria_plat_eth[] = {
++ {
++ .phy = 2,
++ .rxq = 4,
++ .txreadyq = 21,
++ }, {
++ .phy = 1,
++ .rxq = 2,
++ .txreadyq = 19,
++ }
++};
++
++static struct platform_device cambria_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = cambria_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEA,
++ .dev.platform_data = cambria_plat_eth + 1,
++ }
++};
++
++#ifdef CONFIG_LEDS_IXP4XX
++static struct platform_device cambria_leds_pld = {
++ .name = "IXP4XX-PLD-LED",
++ .id = -1,
++ .num_resources = 0,
++};
++
++static struct platform_device cambria_leds_mem = {
++ .name = "IXP4XX-MEM-LED",
++ .id = -1,
++ .num_resources = 0,
++};
++#endif
++
++static struct platform_device *cambria_devices[] __initdata = {
++ &cambria_i2c_gpio,
++ &cambria_flash,
++ &cambria_uart,
++#ifdef CONFIG_LEDS_IXP4XX
++ &cambria_leds_pld,
++ &cambria_leds_mem,
++#endif
++ &cambria_eth[0],
++ &cambria_eth[1],
++};
++
++#ifdef CONFIG_SENSORS_EEPROM
++static int cambria_eeprom_do(struct notifier_block *self, unsigned long event, void *t)
++{
++ struct eeprom_data *data = t;
++ struct sockaddr address;
++ struct net_device * netdev;
++
++ char macs[12];
++
++ /* The MACs are the first 12 bytes in the eeprom at address 0x51 */
++ if (event == EEPROM_REGISTER && data->client.addr == 0x51) {
++ data->attr->read(&data->client.dev.kobj, data->attr, macs, 0, 12);
++ /* eth0 */
++ memcpy(address.sa_data, macs, ETH_ALEN);
++ memcpy(&cambria_plat_eth[0].hwaddr, macs, ETH_ALEN);
++ if ( (netdev = dev_get_by_name(&init_net, "eth0")) )
++ netdev->set_mac_address(netdev, &address);
++
++ /* eth1 */
++ memcpy(address.sa_data, macs + ETH_ALEN, ETH_ALEN);
++ memcpy(&cambria_plat_eth[1].hwaddr, macs + ETH_ALEN, ETH_ALEN);
++ if ( (netdev = dev_get_by_name(&init_net, "eth1")) )
++ netdev->set_mac_address(netdev, &address);
++ }
++
++ return NOTIFY_DONE;
++}
++
++static struct notifier_block cambria_eeprom_notifier = {
++ .notifier_call = cambria_eeprom_do
++};
++#endif
++
++static void __init cambria_init(void)
++{
++ ixp4xx_sys_init();
++
++#ifdef CONFIG_SENSORS_EEPROM
++ register_eeprom_notifier(&cambria_eeprom_notifier);
++#endif
++
++ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
++
++ cambria_pata_resources[0].start = 0x53e00000;
++ cambria_pata_resources[0].end = 0x53e3ffff;
++
++ cambria_pata_resources[1].start = 0x53e40000;
++ cambria_pata_resources[1].end = 0x53e7ffff;
++
++ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
++ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
++
++ platform_device_register(&cambria_pata);
++}
++
++#ifdef CONFIG_MACH_CAMBRIA
++MACHINE_START(CAMBRIA, "Gateworks Cambria series")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = cambria_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.24.5/include/asm-arm/arch-ixp4xx/hardware.h linux-2.6.24.5-owrt/include/asm-arm/arch-ixp4xx/hardware.h
+--- linux-2.6.24.5/include/asm-arm/arch-ixp4xx/hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.24.5-owrt/include/asm-arm/arch-ixp4xx/hardware.h 2008-04-28 21:07:16.000000000 +0200
+@@ -18,7 +18,7 @@
+ #define __ASM_ARCH_HARDWARE_H__
+
+ #define PCIBIOS_MIN_IO 0x00001000
+-#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
++#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x48000000 : 0x48000000)
+
+ /*
+ * We override the standard dma-mask routines for bouncing.
--- /dev/null
+Index: linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c
+===================================================================
+--- linux-2.6.24.2.orig/drivers/net/arm/ixp4xx_eth.c
++++ linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c
+@@ -165,14 +165,15 @@ struct port {
+ struct net_device *netdev;
+ struct napi_struct napi;
+ struct net_device_stats stat;
+- struct mii_if_info mii;
++ struct mii_if_info mii[IXP4XX_ETH_PHY_MAX_ADDR];
+ struct delayed_work mdio_thread;
+ struct eth_plat_info *plat;
+ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
+ struct desc *desc_tab; /* coherent */
+ u32 desc_tab_phys;
+ int id; /* logical port ID */
+- u16 mii_bmcr;
++ u16 mii_bmcr[IXP4XX_ETH_PHY_MAX_ADDR];
++ int phy_count;
+ };
+
+ /* NPE message structure */
+@@ -316,13 +317,14 @@ static void mdio_write(struct net_device
+ spin_unlock_irqrestore(&mdio_lock, flags);
+ }
+
+-static void phy_reset(struct net_device *dev, int phy_id)
++static void phy_reset(struct net_device *dev, int idx)
+ {
+ struct port *port = netdev_priv(dev);
++ int phy_id = port->mii[idx].phy_id;
+ int cycles = 0;
+
+- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
+-
++ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
++
+ while (cycles < MAX_MII_RESET_RETRIES) {
+ if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
+ #if DEBUG_MDIO
+@@ -335,12 +337,12 @@ static void phy_reset(struct net_device
+ cycles++;
+ }
+
+- printk(KERN_ERR "%s: MII reset failed\n", dev->name);
++ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
+ }
+
+-static void eth_set_duplex(struct port *port)
++static void eth_set_duplex(struct port *port, int full_duplex)
+ {
+- if (port->mii.full_duplex)
++ if (full_duplex)
+ __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
+ &port->regs->tx_control[0]);
+ else
+@@ -348,7 +350,7 @@ static void eth_set_duplex(struct port *
+ &port->regs->tx_control[0]);
+ }
+
+-
++#if 0
+ static void phy_check_media(struct port *port, int init)
+ {
+ if (mii_check_media(&port->mii, 1, init))
+@@ -367,7 +369,63 @@ static void phy_check_media(struct port
+ }
+ }
+ }
++#else
++static void phy_update_link(struct net_device *dev, int link)
++{
++ int prev_link = netif_carrier_ok(dev);
++
++ if (!prev_link && link) {
++ printk(KERN_INFO "%s: link up\n", dev->name);
++ netif_carrier_on(dev);
++ } else if (prev_link && !link) {
++ printk(KERN_INFO "%s: link down\n", dev->name);
++ netif_carrier_off(dev);
++ }
++}
++
++static void phy_check_media(struct port *port, int init)
++{
++ struct net_device *dev = port->netdev;
++
++ if (port->phy_count == 1) {
++ struct mii_if_info *mii = &port->mii[0];
++
++ if (mii_check_media(mii, 1, init))
++ eth_set_duplex(port, mii->full_duplex);
++
++ if (mii->force_media) /* mii_check_media() doesn't work */
++ phy_update_link(dev, mii_link_ok(mii));
++ } else {
++ int cur_link = 0;
++ int i;
++
++ if (init)
++ eth_set_duplex(port, 1);
++
++ for (i = 0; i < port->phy_count; i++)
++ cur_link |= mii_link_ok(&port->mii[i]);
++
++ phy_update_link(dev, cur_link);
++ }
++}
++#endif
+
++static void phy_power_down(struct net_device *dev, int idx)
++{
++ struct port *port = netdev_priv(dev);
++ int phy_id = port->mii[idx].phy_id;
++
++ port->mii_bmcr[idx] = mdio_read(dev, phy_id, MII_BMCR) &
++ ~(BMCR_RESET | BMCR_PDOWN);
++ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_PDOWN);
++}
++
++static void phy_power_up(struct net_device *dev, int idx)
++{
++ struct port *port = netdev_priv(dev);
++
++ mdio_write(dev, port->mii[idx].phy_id, MII_BMCR, port->mii_bmcr[idx]);
++}
+
+ static void mdio_thread(struct work_struct *work)
+ {
+@@ -790,9 +848,12 @@ static int eth_ioctl(struct net_device *
+
+ if (!netif_running(dev))
+ return -EINVAL;
+- err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
++ if (port->phy_count != 1)
++ return -EOPNOTSUPP;
++
++ err = generic_mii_ioctl(&port->mii[0], if_mii(req), cmd, &duplex_chg);
+ if (duplex_chg)
+- eth_set_duplex(port);
++ eth_set_duplex(port, port->mii[0].full_duplex);
+ return err;
+ }
+
+@@ -944,7 +1005,8 @@ static int eth_open(struct net_device *d
+ }
+ }
+
+- mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
++ for (i = 0; i < port->phy_count; i++)
++ phy_power_up(dev, i);
+
+ memset(&msg, 0, sizeof(msg));
+ msg.cmd = NPE_VLAN_SETRXQOSENTRY;
+@@ -1103,10 +1165,8 @@ static int eth_close(struct net_device *
+ printk(KERN_CRIT "%s: unable to disable loopback\n",
+ dev->name);
+
+- port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
+- ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
+- mdio_write(dev, port->plat->phy, MII_BMCR,
+- port->mii_bmcr | BMCR_PDOWN);
++ for (i = 0; i < port->phy_count; i++)
++ phy_power_down(dev, i);
+
+ if (!ports_open)
+ qmgr_disable_irq(TXDONE_QUEUE);
+@@ -1117,6 +1177,42 @@ static int eth_close(struct net_device *
+ return 0;
+ }
+
++static void eth_add_phy(struct net_device *dev, int phy_id)
++{
++ struct port *port = netdev_priv(dev);
++ int i;
++
++ i = port->phy_count++;
++
++ port->mii[i].dev = dev;
++ port->mii[i].mdio_read = mdio_read;
++ port->mii[i].mdio_write = mdio_write;
++ port->mii[i].phy_id = phy_id;
++ port->mii[i].phy_id_mask = 0x1F;
++ port->mii[i].reg_num_mask = 0x1F;
++
++ printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, phy_id,
++ npe_name(port->npe));
++
++ phy_reset(dev, i);
++ phy_power_down(dev, i);
++}
++
++static void eth_init_mii(struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++
++ if (port->plat->phy < IXP4XX_ETH_PHY_MAX_ADDR) {
++ eth_add_phy(dev, port->plat->phy);
++ } else {
++ int i;
++ for (i = 0; i < IXP4XX_ETH_PHY_MAX_ADDR; i++)
++ if (port->plat->phy_mask & (1U << i))
++ eth_add_phy(dev, i);
++ }
++
++}
++
+ static int __devinit eth_init_one(struct platform_device *pdev)
+ {
+ struct port *port;
+@@ -1189,20 +1285,7 @@ static int __devinit eth_init_one(struct
+ __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
+ udelay(50);
+
+- port->mii.dev = dev;
+- port->mii.mdio_read = mdio_read;
+- port->mii.mdio_write = mdio_write;
+- port->mii.phy_id = plat->phy;
+- port->mii.phy_id_mask = 0x1F;
+- port->mii.reg_num_mask = 0x1F;
+-
+- printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
+- npe_name(port->npe));
+-
+- phy_reset(dev, plat->phy);
+- port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
+- ~(BMCR_RESET | BMCR_PDOWN);
+- mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
++ eth_init_mii(dev);
+
+ INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
+ return 0;
+Index: linux-2.6.24.2/include/asm-arm/arch-ixp4xx/platform.h
+===================================================================
+--- linux-2.6.24.2.orig/include/asm-arm/arch-ixp4xx/platform.h
++++ linux-2.6.24.2/include/asm-arm/arch-ixp4xx/platform.h
+@@ -106,12 +106,15 @@ struct sys_timer;
+ #define IXP4XX_ETH_NPEB 0x10
+ #define IXP4XX_ETH_NPEC 0x20
+
++#define IXP4XX_ETH_PHY_MAX_ADDR 32
++
+ /* Information about built-in Ethernet MAC interfaces */
+ struct eth_plat_info {
+ u8 phy; /* MII PHY ID, 0 - 31 */
+ u8 rxq; /* configurable, currently 0 - 31 only */
+ u8 txreadyq;
+ u8 hwaddr[6];
++ u32 phy_mask;
+ };
+
+ /* Information about built-in HSS (synchronous serial) interfaces */
+++ /dev/null
-diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
-index a3df09e..94e7aa7 100644
---- a/drivers/net/wan/Kconfig
-+++ b/drivers/net/wan/Kconfig
-@@ -334,6 +334,15 @@ config DSCC4_PCI_RST
-
- Say Y if your card supports this feature.
-
-+config IXP4XX_HSS
-+ tristate "IXP4xx HSS (synchronous serial port) support"
-+ depends on HDLC && ARM && ARCH_IXP4XX
-+ select IXP4XX_NPE
-+ select IXP4XX_QMGR
-+ help
-+ Say Y here if you want to use built-in HSS ports
-+ on IXP4xx processor.
-+
- config DLCI
- tristate "Frame Relay DLCI support"
- ---help---
-diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
-index d61fef3..1b1d116 100644
---- a/drivers/net/wan/Makefile
-+++ b/drivers/net/wan/Makefile
-@@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
- obj-$(CONFIG_WANXL) += wanxl.o
- obj-$(CONFIG_PCI200SYN) += pci200syn.o
- obj-$(CONFIG_PC300TOO) += pc300too.o
-+obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
-
- clean-files := wanxlfw.inc
- $(obj)/wanxl.o: $(obj)/wanxlfw.inc
-diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
-new file mode 100644
-index 0000000..cf971b3
---- /dev/null
-+++ b/drivers/net/wan/ixp4xx_hss.c
-@@ -0,0 +1,2886 @@
-+/*
-+ * Intel IXP4xx HSS (synchronous serial port) driver for Linux
-+ *
-+ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License
-+ * as published by the Free Software Foundation.
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/cdev.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
-+#include <linux/fs.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/hdlc.h>
-+#include <linux/platform_device.h>
-+#include <linux/poll.h>
-+#include <asm/arch/npe.h>
-+#include <asm/arch/qmgr.h>
-+
-+#define DEBUG_QUEUES 0
-+#define DEBUG_DESC 0
-+#define DEBUG_RX 0
-+#define DEBUG_TX 0
-+#define DEBUG_PKT_BYTES 0
-+#define DEBUG_CLOSE 0
-+#define DEBUG_FRAMER 0
-+
-+#define DRV_NAME "ixp4xx_hss"
-+
-+#define PKT_EXTRA_FLAGS 0 /* orig 1 */
-+#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
-+#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
-+#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
-+
-+#define RX_DESCS 16 /* also length of all RX queues */
-+#define TX_DESCS 16 /* also length of all TX queues */
-+
-+#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
-+#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
-+#define MAX_CLOSE_WAIT 1000 /* microseconds */
-+#define HSS_COUNT 2
-+#define MIN_FRAME_SIZE 16 /* bits */
-+#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
-+#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
-+#define MAX_CHAN_DEVICES 32
-+#define CHANNEL_HDLC 0xFE
-+#define CHANNEL_UNUSED 0xFF
-+
-+#define NAPI_WEIGHT 16
-+#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
-+#define CHAN_RX_FRAMES 64
-+#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
-+#define CHAN_TX_LIST_FRAMES 16 /* bytes/channel per list, 16 - 48 */
-+#define CHAN_TX_LISTS 8
-+#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
-+#define CHAN_QUEUE_LEN 16 /* minimum possible */
-+
-+
-+/* Queue IDs */
-+#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
-+#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
-+#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
-+#define HSS0_PKT_TX1_QUEUE 15
-+#define HSS0_PKT_TX2_QUEUE 16
-+#define HSS0_PKT_TX3_QUEUE 17
-+#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
-+#define HSS0_PKT_RXFREE1_QUEUE 19
-+#define HSS0_PKT_RXFREE2_QUEUE 20
-+#define HSS0_PKT_RXFREE3_QUEUE 21
-+#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
-+
-+#define HSS1_CHL_RXTRIG_QUEUE 10
-+#define HSS1_PKT_RX_QUEUE 0
-+#define HSS1_PKT_TX0_QUEUE 5
-+#define HSS1_PKT_TX1_QUEUE 6
-+#define HSS1_PKT_TX2_QUEUE 7
-+#define HSS1_PKT_TX3_QUEUE 8
-+#define HSS1_PKT_RXFREE0_QUEUE 1
-+#define HSS1_PKT_RXFREE1_QUEUE 2
-+#define HSS1_PKT_RXFREE2_QUEUE 3
-+#define HSS1_PKT_RXFREE3_QUEUE 4
-+#define HSS1_PKT_TXDONE_QUEUE 9
-+
-+#define NPE_PKT_MODE_HDLC 0
-+#define NPE_PKT_MODE_RAW 1
-+#define NPE_PKT_MODE_56KMODE 2
-+#define NPE_PKT_MODE_56KENDIAN_MSB 4
-+
-+/* PKT_PIPE_HDLC_CFG_WRITE flags */
-+#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
-+#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
-+#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
-+
-+
-+/* hss_config, PCRs */
-+/* Frame sync sampling, default = active low */
-+#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
-+#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
-+#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
-+
-+/* Frame sync pin: input (default) or output generated off a given clk edge */
-+#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
-+#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
-+
-+/* Frame and data clock sampling on edge, default = falling */
-+#define PCR_FCLK_EDGE_RISING 0x08000000
-+#define PCR_DCLK_EDGE_RISING 0x04000000
-+
-+/* Clock direction, default = input */
-+#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
-+
-+/* Generate/Receive frame pulses, default = enabled */
-+#define PCR_FRM_PULSE_DISABLED 0x01000000
-+
-+ /* Data rate is full (default) or half the configured clk speed */
-+#define PCR_HALF_CLK_RATE 0x00200000
-+
-+/* Invert data between NPE and HSS FIFOs? (default = no) */
-+#define PCR_DATA_POLARITY_INVERT 0x00100000
-+
-+/* TX/RX endianness, default = LSB */
-+#define PCR_MSB_ENDIAN 0x00080000
-+
-+/* Normal (default) / open drain mode (TX only) */
-+#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
-+
-+/* No framing bit transmitted and expected on RX? (default = framing bit) */
-+#define PCR_SOF_NO_FBIT 0x00020000
-+
-+/* Drive data pins? */
-+#define PCR_TX_DATA_ENABLE 0x00010000
-+
-+/* Voice 56k type: drive the data pins low (default), high, high Z */
-+#define PCR_TX_V56K_HIGH 0x00002000
-+#define PCR_TX_V56K_HIGH_IMP 0x00004000
-+
-+/* Unassigned type: drive the data pins low (default), high, high Z */
-+#define PCR_TX_UNASS_HIGH 0x00000800
-+#define PCR_TX_UNASS_HIGH_IMP 0x00001000
-+
-+/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
-+#define PCR_TX_FB_HIGH_IMP 0x00000400
-+
-+/* 56k data endiannes - which bit unused: high (default) or low */
-+#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
-+
-+/* 56k data transmission type: 32/8 bit data (default) or 56K data */
-+#define PCR_TX_56KS_56K_DATA 0x00000100
-+
-+/* hss_config, cCR */
-+/* Number of packetized clients, default = 1 */
-+#define CCR_NPE_HFIFO_2_HDLC 0x04000000
-+#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
-+
-+/* default = no loopback */
-+#define CCR_LOOPBACK 0x02000000
-+
-+/* HSS number, default = 0 (first) */
-+#define CCR_SECOND_HSS 0x01000000
-+
-+
-+/* hss_config, clkCR: main:10, num:10, denom:12 */
-+#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
-+
-+#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
-+#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
-+#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
-+#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
-+#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
-+#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
-+
-+#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
-+#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
-+#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
-+#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
-+#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
-+#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
-+
-+
-+/* hss_config, LUT entries */
-+#define TDMMAP_UNASSIGNED 0
-+#define TDMMAP_HDLC 1 /* HDLC - packetized */
-+#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
-+#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
-+
-+/* offsets into HSS config */
-+#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
-+#define HSS_CONFIG_RX_PCR 0x04
-+#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
-+#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
-+#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
-+#define HSS_CONFIG_RX_FCR 0x14
-+#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
-+#define HSS_CONFIG_RX_LUT 0x38
-+
-+
-+/* NPE command codes */
-+/* writes the ConfigWord value to the location specified by offset */
-+#define PORT_CONFIG_WRITE 0x40
-+
-+/* triggers the NPE to load the contents of the configuration table */
-+#define PORT_CONFIG_LOAD 0x41
-+
-+/* triggers the NPE to return an HssErrorReadResponse message */
-+#define PORT_ERROR_READ 0x42
-+
-+/* reset NPE internal status and enable the HssChannelized operation */
-+#define CHAN_FLOW_ENABLE 0x43
-+#define CHAN_FLOW_DISABLE 0x44
-+#define CHAN_IDLE_PATTERN_WRITE 0x45
-+#define CHAN_NUM_CHANS_WRITE 0x46
-+#define CHAN_RX_BUF_ADDR_WRITE 0x47
-+#define CHAN_RX_BUF_CFG_WRITE 0x48
-+#define CHAN_TX_BLK_CFG_WRITE 0x49
-+#define CHAN_TX_BUF_ADDR_WRITE 0x4A
-+#define CHAN_TX_BUF_SIZE_WRITE 0x4B
-+#define CHAN_TSLOTSWITCH_ENABLE 0x4C
-+#define CHAN_TSLOTSWITCH_DISABLE 0x4D
-+
-+/* downloads the gainWord value for a timeslot switching channel associated
-+ with bypassNum */
-+#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
-+
-+/* triggers the NPE to reset internal status and enable the HssPacketized
-+ operation for the flow specified by pPipe */
-+#define PKT_PIPE_FLOW_ENABLE 0x50
-+#define PKT_PIPE_FLOW_DISABLE 0x51
-+#define PKT_NUM_PIPES_WRITE 0x52
-+#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
-+#define PKT_PIPE_HDLC_CFG_WRITE 0x54
-+#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
-+#define PKT_PIPE_RX_SIZE_WRITE 0x56
-+#define PKT_PIPE_MODE_WRITE 0x57
-+
-+/* HDLC packet status values - desc->status */
-+#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
-+#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
-+#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
-+#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
-+ this packet (if buf_len < pkt_len) */
-+#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
-+#define ERR_HDLC_ABORT 6 /* abort sequence received */
-+#define ERR_DISCONNECTING 7 /* disconnect is in progress */
-+
-+
-+enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
-+enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
-+enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
-+
-+#ifdef __ARMEB__
-+typedef struct sk_buff buffer_t;
-+#define free_buffer dev_kfree_skb
-+#define free_buffer_irq dev_kfree_skb_irq
-+#else
-+typedef void buffer_t;
-+#define free_buffer kfree
-+#define free_buffer_irq kfree
-+#endif
-+
-+struct chan_device {
-+ struct cdev cdev;
-+ struct device *dev;
-+ struct port *port;
-+ unsigned int open_count, excl_open;
-+ unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
-+ unsigned long errors_bitmap;
-+ u8 id, chan_count;
-+ u8 log_channels[MAX_CHANNELS];
-+};
-+
-+struct port {
-+ struct device *dev;
-+ struct npe *npe;
-+ struct net_device *netdev;
-+ struct napi_struct napi;
-+ struct hss_plat_info *plat;
-+ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
-+ struct desc *desc_tab; /* coherent */
-+ u32 desc_tab_phys;
-+ unsigned int id;
-+ atomic_t chan_tx_irq_number, chan_rx_irq_number;
-+ wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
-+ u8 hdlc_cfg;
-+
-+ /* the following fields must be protected by npe_lock */
-+ enum mode mode;
-+ unsigned int clock_type, clock_rate, loopback;
-+ unsigned int frame_size, frame_sync_offset;
-+
-+ struct chan_device *chan_devices[MAX_CHAN_DEVICES];
-+ u8 *chan_buf;
-+ u32 chan_tx_buf_phys, chan_rx_buf_phys;
-+ unsigned int chan_open_count, hdlc_open;
-+ unsigned int chan_started, initialized, just_set_offset;
-+ enum alignment aligned, carrier;
-+ unsigned int chan_last_rx, chan_last_tx;
-+ /* assigned channels, may be invalid with given frame length or mode */
-+ u8 channels[MAX_CHANNELS];
-+ int msg_count;
-+};
-+
-+/* NPE message structure */
-+struct msg {
-+#ifdef __ARMEB__
-+ u8 cmd, unused, hss_port, index;
-+ union {
-+ struct { u8 data8a, data8b, data8c, data8d; };
-+ struct { u16 data16a, data16b; };
-+ struct { u32 data32; };
-+ };
-+#else
-+ u8 index, hss_port, unused, cmd;
-+ union {
-+ struct { u8 data8d, data8c, data8b, data8a; };
-+ struct { u16 data16b, data16a; };
-+ struct { u32 data32; };
-+ };
-+#endif
-+};
-+
-+/* HDLC packet descriptor */
-+struct desc {
-+ u32 next; /* pointer to next buffer, unused */
-+
-+#ifdef __ARMEB__
-+ u16 buf_len; /* buffer length */
-+ u16 pkt_len; /* packet length */
-+ u32 data; /* pointer to data buffer in RAM */
-+ u8 status;
-+ u8 error_count;
-+ u16 __reserved;
-+#else
-+ u16 pkt_len; /* packet length */
-+ u16 buf_len; /* buffer length */
-+ u32 data; /* pointer to data buffer in RAM */
-+ u16 __reserved;
-+ u8 error_count;
-+ u8 status;
-+#endif
-+ u32 __reserved1[4];
-+};
-+
-+
-+#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
-+ (n) * sizeof(struct desc))
-+#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
-+
-+#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
-+ ((n) + RX_DESCS) * sizeof(struct desc))
-+#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
-+
-+#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES)
-+#define chan_tx_lists_len(port) (port->frame_size / 8 * CHAN_TX_LISTS * \
-+ sizeof(u32))
-+#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES)
-+
-+#define chan_tx_buf(port) ((port)->chan_buf)
-+#define chan_tx_lists(port) (chan_tx_buf(port) + chan_tx_buf_len(port))
-+#define chan_rx_buf(port) (chan_tx_lists(port) + chan_tx_lists_len(port))
-+
-+#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys + \
-+ chan_tx_buf_len(port))
-+
-+static int hss_prepare_chan(struct port *port);
-+void hss_chan_stop(struct port *port);
-+
-+/*****************************************************************************
-+ * global variables
-+ ****************************************************************************/
-+
-+static struct class *hss_class;
-+static int chan_major;
-+static int ports_open;
-+static struct dma_pool *dma_pool;
-+static spinlock_t npe_lock;
-+
-+static const struct {
-+ int tx, txdone, rx, rxfree, chan;
-+}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
-+ HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
-+ {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
-+ HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
-+};
-+
-+/*****************************************************************************
-+ * utility functions
-+ ****************************************************************************/
-+
-+static inline struct port* dev_to_port(struct net_device *dev)
-+{
-+ return dev_to_hdlc(dev)->priv;
-+}
-+
-+static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
-+{
-+ return container_of(inode->i_cdev, struct chan_device, cdev);
-+}
-+
-+#ifndef __ARMEB__
-+static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
-+{
-+ int i;
-+ for (i = 0; i < cnt; i++)
-+ dest[i] = swab32(src[i]);
-+}
-+#endif
-+
-+static int get_number(const char **buf, size_t *len, unsigned int *ptr,
-+ unsigned int min, unsigned int max)
-+{
-+ char *endp;
-+ unsigned long val = simple_strtoul(*buf, &endp, 10);
-+
-+ if (endp == *buf || endp - *buf > *len || val < min || val > max)
-+ return -EINVAL;
-+ *len -= endp - *buf;
-+ *buf = endp;
-+ *ptr = val;
-+ return 0;
-+}
-+
-+static int parse_channels(const char **buf, size_t *len, u8 *channels)
-+{
-+ unsigned int ch, next = 0;
-+
-+ if (*len && (*buf)[*len - 1] == '\n')
-+ (*len)--;
-+
-+ memset(channels, 0, MAX_CHANNELS);
-+
-+ if (!*len)
-+ return 0;
-+
-+ /* Format: "A,B-C,...", A > B > C */
-+ while (1) {
-+ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
-+ return -EINVAL;
-+ channels[ch] = 1;
-+ next = ch + 1;
-+ if (!*len)
-+ break;
-+ if (**buf == ',') {
-+ (*buf)++;
-+ (*len)--;
-+ continue;
-+ }
-+ if (**buf != '-')
-+ return -EINVAL;
-+ (*buf)++;
-+ (*len)--;
-+ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
-+ return -EINVAL;
-+ while (next <= ch)
-+ channels[next++] = 1;
-+ if (!*len)
-+ break;
-+ if (**buf != ',')
-+ return -EINVAL;
-+ (*buf)++;
-+ (*len)--;
-+ }
-+ return 1;
-+}
-+
-+static size_t print_channels(struct port *port, char *buf, u8 id)
-+{
-+ unsigned int ch, cnt = 0;
-+ size_t len = 0;
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (port->channels[ch] == id) {
-+ if (cnt == 0) {
-+ sprintf(buf + len, "%s%u", len ? "," : "", ch);
-+ len += strlen(buf + len);
-+ }
-+ cnt++;
-+ } else {
-+ if (cnt > 1) {
-+ sprintf(buf + len, "-%u", ch - 1);
-+ len += strlen(buf + len);
-+ }
-+ cnt = 0;
-+ }
-+ if (cnt > 1) {
-+ sprintf(buf + len, "-%u", ch - 1);
-+ len += strlen(buf + len);
-+ }
-+
-+ buf[len++] = '\n';
-+ return len;
-+}
-+
-+static inline unsigned int sub_offset(unsigned int a, unsigned int b,
-+ unsigned int modulo)
-+{
-+ return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
-+}
-+
-+/*****************************************************************************
-+ * HSS access
-+ ****************************************************************************/
-+
-+static void hss_config_load(struct port *port)
-+{
-+ struct msg msg;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_LOAD;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
-+ break;
-+ if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
-+ break;
-+
-+ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
-+ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
-+ break;
-+
-+ /* HDLC may stop working without this */
-+ npe_recv_message(port->npe, &msg, "FLUSH_IT");
-+ return;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
-+ port->id);
-+ BUG();
-+}
-+
-+static void hss_config_set_pcr(struct port *port)
-+{
-+ struct msg msg;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_TX_PCR;
-+ msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
-+ PCR_TX_DATA_ENABLE;
-+ if (port->frame_size % 8 == 0)
-+ msg.data32 |= PCR_SOF_NO_FBIT;
-+ if (port->clock_type == CLOCK_INT)
-+ msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
-+ break;
-+
-+ msg.index = HSS_CONFIG_RX_PCR;
-+ msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
-+ break;
-+ return;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
-+ BUG();
-+}
-+
-+static void hss_config_set_hdlc_cfg(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = port->hdlc_cfg; /* rx_cfg */
-+ msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
-+ " configuration\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_core(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_CORE_CR;
-+ msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
-+ (port->id ? CCR_SECOND_HSS : 0);
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
-+ " register\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_line(struct port *port)
-+{
-+ struct msg msg;
-+
-+ hss_config_set_pcr(port);
-+ hss_config_set_core(port);
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_CLOCK_CR;
-+ msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
-+ " register\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_rx_frame(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_RX_FCR;
-+ msg.data16a = port->frame_sync_offset;
-+ msg.data16b = port->frame_size - 1;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
-+ " and offset\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_frame(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_TX_FCR;
-+ msg.data16a = TX_FRAME_SYNC_OFFSET;
-+ msg.data16b = port->frame_size - 1;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
-+ " and offset\n", port->id);
-+ BUG();
-+ }
-+ hss_config_set_rx_frame(port);
-+}
-+
-+static void hss_config_set_lut(struct port *port)
-+{
-+ struct msg msg;
-+ int chan_count = 0, log_chan = 0, i, ch;
-+ u32 lut[MAX_CHANNELS / 4];
-+
-+ memset(lut, 0, sizeof(lut));
-+ for (i = 0; i < MAX_CHAN_DEVICES; i++)
-+ if (port->chan_devices[i])
-+ port->chan_devices[i]->chan_count = 0;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++) {
-+ struct chan_device *chdev = NULL;
-+ unsigned int entry;
-+
-+ if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
-+ chdev = port->chan_devices[port->channels[ch]];
-+
-+ if (port->mode == MODE_G704 && ch == 0)
-+ entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
-+ else if (port->mode == MODE_HDLC ||
-+ port->channels[ch] == CHANNEL_HDLC)
-+ entry = TDMMAP_HDLC;
-+ else if (chdev && chdev->open_count) {
-+ entry = TDMMAP_VOICE64K;
-+ chdev->log_channels[chdev->chan_count++] = log_chan;
-+ } else
-+ entry = TDMMAP_UNASSIGNED;
-+ if (entry == TDMMAP_VOICE64K) {
-+ chan_count++;
-+ log_chan++;
-+ }
-+
-+ msg.data32 >>= 2;
-+ msg.data32 |= entry << 30;
-+
-+ if (ch % 16 == 15) {
-+ msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
-+ break;
-+
-+ msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
-+ break;
-+ }
-+ }
-+ if (ch != MAX_CHANNELS) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
-+ " table\n", port->id);
-+ BUG();
-+ }
-+
-+ hss_config_set_frame(port);
-+
-+ if (!chan_count)
-+ return;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_NUM_CHANS_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = chan_count;
-+ if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
-+ port->id);
-+ BUG();
-+ }
-+
-+ /* don't leak data */
-+ // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
-+ if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
-+ for (i = 0; i < CHAN_TX_FRAMES; i += 4)
-+ *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
-+
-+ for (i = 0; i < CHAN_TX_LISTS; i++) {
-+ u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
-+ u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
-+ for (ch = 0; ch < chan_count; ch++)
-+ list[ch] = phys + ch * CHAN_TX_FRAMES;
-+ }
-+ dma_sync_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port) + chan_tx_lists_len(port),
-+ DMA_TO_DEVICE);
-+}
-+
-+static u32 hss_config_get_status(struct port *port)
-+{
-+ struct msg msg;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_ERROR_READ;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
-+ break;
-+ if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
-+ break;
-+
-+ return msg.data32;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
-+ BUG();
-+}
-+
-+static void hss_config_start_chan(struct port *port)
-+{
-+ struct msg msg;
-+
-+ port->chan_last_tx = 0;
-+ port->chan_last_rx = 0;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data32 = port->chan_rx_buf_phys;
-+ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data32 = chan_tx_lists_phys(port);
-+ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_FLOW_ENABLE;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
-+ break;
-+ port->chan_started = 1;
-+ return;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
-+ port->id);
-+ BUG();
-+}
-+
-+static void hss_config_stop_chan(struct port *port)
-+{
-+ struct msg msg;
-+
-+ if (!port->chan_started)
-+ return;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_FLOW_DISABLE;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
-+ port->id);
-+ BUG();
-+ }
-+ hss_config_get_status(port); /* make sure it's halted */
-+}
-+
-+static void hss_config_start_hdlc(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_PIPE_FLOW_ENABLE;
-+ msg.hss_port = port->id;
-+ msg.data32 = 0;
-+ if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
-+ port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_stop_hdlc(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_PIPE_FLOW_DISABLE;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
-+ port->id);
-+ BUG();
-+ }
-+ hss_config_get_status(port); /* make sure it's halted */
-+}
-+
-+static int hss_config_load_firmware(struct port *port)
-+{
-+ struct msg msg;
-+
-+ if (port->initialized)
-+ return 0;
-+
-+ if (!npe_running(port->npe)) {
-+ int err;
-+ if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
-+ port->dev)))
-+ return err;
-+ }
-+
-+ do {
-+ /* HSS main configuration */
-+ hss_config_set_line(port);
-+
-+ hss_config_set_frame(port);
-+
-+ /* HDLC mode configuration */
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_NUM_PIPES_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = PKT_NUM_PIPES;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
-+ msg.data8a = PKT_PIPE_FIFO_SIZEW;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_MODE_WRITE;
-+ msg.data8a = NPE_PKT_MODE_HDLC;
-+ /* msg.data8b = inv_mask */
-+ /* msg.data8c = or_mask */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
-+ msg.data16a = HDLC_MAX_MRU; /* including CRC */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
-+ msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
-+ break;
-+
-+ /* Channelized operation settings */
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_TX_BLK_CFG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
-+ msg.data8a = msg.data8b / 4;
-+ msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
-+ msg.data8c = msg.data8d / 4;
-+ if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_RX_BUF_CFG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = CHAN_RX_TRIGGER / 8;
-+ msg.data8b = CHAN_RX_FRAMES;
-+ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = CHAN_TX_LISTS;
-+ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
-+ break;
-+
-+ port->initialized = 1;
-+ return 0;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
-+ BUG();
-+}
-+
-+/*****************************************************************************
-+ * packetized (HDLC) operation
-+ ****************************************************************************/
-+
-+static inline void debug_pkt(struct net_device *dev, const char *func,
-+ u8 *data, int len)
-+{
-+#if DEBUG_PKT_BYTES
-+ int i;
-+
-+ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
-+ for (i = 0; i < len; i++) {
-+ if (i >= DEBUG_PKT_BYTES)
-+ break;
-+ printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
-+ }
-+ printk(KERN_DEBUG "\n");
-+#endif
-+}
-+
-+
-+static inline void debug_desc(u32 phys, struct desc *desc)
-+{
-+#if DEBUG_DESC
-+ printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
-+ phys, desc->next, desc->buf_len, desc->pkt_len,
-+ desc->data, desc->status, desc->error_count);
-+#endif
-+}
-+
-+static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
-+{
-+#if DEBUG_QUEUES
-+ static struct {
-+ int queue;
-+ char *name;
-+ } names[] = {
-+ { HSS0_PKT_TX0_QUEUE, "TX#0 " },
-+ { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
-+ { HSS0_PKT_RX_QUEUE, "RX#0 " },
-+ { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
-+ { HSS1_PKT_TX0_QUEUE, "TX#1 " },
-+ { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
-+ { HSS1_PKT_RX_QUEUE, "RX#1 " },
-+ { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
-+ };
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(names); i++)
-+ if (names[i].queue == queue)
-+ break;
-+
-+ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
-+ i < ARRAY_SIZE(names) ? names[i].name : "",
-+ is_get ? "->" : "<-", phys);
-+#endif
-+}
-+
-+static inline u32 queue_get_entry(unsigned int queue)
-+{
-+ u32 phys = qmgr_get_entry(queue);
-+ debug_queue(queue, 1, phys);
-+ return phys;
-+}
-+
-+static inline int queue_get_desc(unsigned int queue, struct port *port,
-+ int is_tx)
-+{
-+ u32 phys, tab_phys, n_desc;
-+ struct desc *tab;
-+
-+ if (!(phys = queue_get_entry(queue)))
-+ return -1;
-+
-+ BUG_ON(phys & 0x1F);
-+ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
-+ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
-+ n_desc = (phys - tab_phys) / sizeof(struct desc);
-+ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
-+ debug_desc(phys, &tab[n_desc]);
-+ BUG_ON(tab[n_desc].next);
-+ return n_desc;
-+}
-+
-+static inline void queue_put_desc(unsigned int queue, u32 phys,
-+ struct desc *desc)
-+{
-+ debug_queue(queue, 0, phys);
-+ debug_desc(phys, desc);
-+ BUG_ON(phys & 0x1F);
-+ qmgr_put_entry(queue, phys);
-+ BUG_ON(qmgr_stat_overflow(queue));
-+}
-+
-+
-+static inline void dma_unmap_tx(struct port *port, struct desc *desc)
-+{
-+#ifdef __ARMEB__
-+ dma_unmap_single(&port->netdev->dev, desc->data,
-+ desc->buf_len, DMA_TO_DEVICE);
-+#else
-+ dma_unmap_single(&port->netdev->dev, desc->data & ~3,
-+ ALIGN((desc->data & 3) + desc->buf_len, 4),
-+ DMA_TO_DEVICE);
-+#endif
-+}
-+
-+
-+static void hss_hdlc_set_carrier(void *pdev, int carrier)
-+{
-+ struct net_device *netdev = pdev;
-+ struct port *port = dev_to_port(netdev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ port->carrier = carrier;
-+ if (!port->loopback) {
-+ if (carrier)
-+ netif_carrier_on(netdev);
-+ else
-+ netif_carrier_off(netdev);
-+ }
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+}
-+
-+static void hss_hdlc_rx_irq(void *pdev)
-+{
-+ struct net_device *dev = pdev;
-+ struct port *port = dev_to_port(dev);
-+
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
-+#endif
-+ qmgr_disable_irq(queue_ids[port->id].rx);
-+ netif_rx_schedule(dev, &port->napi);
-+}
-+
-+static int hss_hdlc_poll(struct napi_struct *napi, int budget)
-+{
-+ struct port *port = container_of(napi, struct port, napi);
-+ struct net_device *dev = port->netdev;
-+ unsigned int rxq = queue_ids[port->id].rx;
-+ unsigned int rxfreeq = queue_ids[port->id].rxfree;
-+ struct net_device_stats *stats = hdlc_stats(dev);
-+ int received = 0;
-+
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
-+#endif
-+
-+ while (received < budget) {
-+ struct sk_buff *skb;
-+ struct desc *desc;
-+ int n;
-+#ifdef __ARMEB__
-+ struct sk_buff *temp;
-+ u32 phys;
-+#endif
-+
-+ if ((n = queue_get_desc(rxq, port, 0)) < 0) {
-+ received = 0; /* No packet received */
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll"
-+ " netif_rx_complete\n", dev->name);
-+#endif
-+ netif_rx_complete(dev, napi);
-+ qmgr_enable_irq(rxq);
-+ if (!qmgr_stat_empty(rxq) &&
-+ netif_rx_reschedule(dev, napi)) {
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll"
-+ " netif_rx_reschedule succeeded\n",
-+ dev->name);
-+#endif
-+ qmgr_disable_irq(rxq);
-+ continue;
-+ }
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
-+ dev->name);
-+#endif
-+ return 0; /* all work done */
-+ }
-+
-+ desc = rx_desc_ptr(port, n);
-+#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
-+ if (desc->error_count)
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
-+ " errors %u\n", dev->name, desc->status,
-+ desc->error_count);
-+#endif
-+ skb = NULL;
-+ switch (desc->status) {
-+ case 0:
-+#ifdef __ARMEB__
-+ if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
-+ phys = dma_map_single(&dev->dev, skb->data,
-+ RX_SIZE,
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(phys)) {
-+ dev_kfree_skb(skb);
-+ skb = NULL;
-+ }
-+ }
-+#else
-+ skb = netdev_alloc_skb(dev, desc->pkt_len);
-+#endif
-+ if (!skb)
-+ stats->rx_dropped++;
-+ break;
-+ case ERR_HDLC_ALIGN:
-+ case ERR_HDLC_ABORT:
-+ stats->rx_frame_errors++;
-+ stats->rx_errors++;
-+ break;
-+ case ERR_HDLC_FCS:
-+ stats->rx_crc_errors++;
-+ stats->rx_errors++;
-+ break;
-+ case ERR_HDLC_TOO_LONG:
-+ stats->rx_length_errors++;
-+ stats->rx_errors++;
-+ break;
-+ default: /* FIXME - remove printk */
-+ printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
-+ " errors %u\n", dev->name, desc->status,
-+ desc->error_count);
-+ stats->rx_errors++;
-+ }
-+
-+ if (!skb) {
-+ /* put the desc back on RX-ready queue */
-+ desc->buf_len = RX_SIZE;
-+ desc->pkt_len = desc->status = 0;
-+ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
-+ continue;
-+ }
-+
-+ /* process received frame */
-+#ifdef __ARMEB__
-+ temp = skb;
-+ skb = port->rx_buff_tab[n];
-+ dma_unmap_single(&dev->dev, desc->data,
-+ RX_SIZE, DMA_FROM_DEVICE);
-+#else
-+ dma_sync_single(&dev->dev, desc->data,
-+ RX_SIZE, DMA_FROM_DEVICE);
-+ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
-+ ALIGN(desc->pkt_len, 4) / 4);
-+#endif
-+ skb_put(skb, desc->pkt_len);
-+
-+ debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
-+
-+ skb->protocol = hdlc_type_trans(skb, dev);
-+ dev->last_rx = jiffies;
-+ stats->rx_packets++;
-+ stats->rx_bytes += skb->len;
-+ netif_receive_skb(skb);
-+
-+ /* put the new buffer on RX-free queue */
-+#ifdef __ARMEB__
-+ port->rx_buff_tab[n] = temp;
-+ desc->data = phys;
-+#endif
-+ desc->buf_len = RX_SIZE;
-+ desc->pkt_len = 0;
-+ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
-+ received++;
-+ }
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
-+#endif
-+ return received; /* not all work done */
-+}
-+
-+
-+static void hss_hdlc_txdone_irq(void *pdev)
-+{
-+ struct net_device *dev = pdev;
-+ struct port *port = dev_to_port(dev);
-+ struct net_device_stats *stats = hdlc_stats(dev);
-+ int n_desc;
-+
-+#if DEBUG_TX
-+ printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
-+#endif
-+ while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
-+ port, 1)) >= 0) {
-+ struct desc *desc;
-+ int start;
-+
-+ desc = tx_desc_ptr(port, n_desc);
-+
-+ stats->tx_packets++;
-+ stats->tx_bytes += desc->pkt_len;
-+
-+ dma_unmap_tx(port, desc);
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
-+ dev->name, port->tx_buff_tab[n_desc]);
-+#endif
-+ free_buffer_irq(port->tx_buff_tab[n_desc]);
-+ port->tx_buff_tab[n_desc] = NULL;
-+
-+ start = qmgr_stat_empty(port->plat->txreadyq);
-+ queue_put_desc(port->plat->txreadyq,
-+ tx_desc_phys(port, n_desc), desc);
-+ if (start) {
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
-+ " ready\n", dev->name);
-+#endif
-+ netif_wake_queue(dev);
-+ }
-+ }
-+}
-+
-+static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct port *port = dev_to_port(dev);
-+ struct net_device_stats *stats = hdlc_stats(dev);
-+ unsigned int txreadyq = port->plat->txreadyq;
-+ int len, offset, bytes, n;
-+ void *mem;
-+ u32 phys;
-+ struct desc *desc;
-+
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
-+#endif
-+
-+ if (unlikely(skb->len > HDLC_MAX_MRU)) {
-+ dev_kfree_skb(skb);
-+ stats->tx_errors++;
-+ return NETDEV_TX_OK;
-+ }
-+
-+ debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
-+
-+ len = skb->len;
-+#ifdef __ARMEB__
-+ offset = 0; /* no need to keep alignment */
-+ bytes = len;
-+ mem = skb->data;
-+#else
-+ offset = (int)skb->data & 3; /* keep 32-bit alignment */
-+ bytes = ALIGN(offset + len, 4);
-+ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
-+ dev_kfree_skb(skb);
-+ stats->tx_dropped++;
-+ return NETDEV_TX_OK;
-+ }
-+ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
-+ dev_kfree_skb(skb);
-+#endif
-+
-+ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
-+ if (dma_mapping_error(phys)) {
-+#ifdef __ARMEB__
-+ dev_kfree_skb(skb);
-+#else
-+ kfree(mem);
-+#endif
-+ stats->tx_dropped++;
-+ return NETDEV_TX_OK;
-+ }
-+
-+ n = queue_get_desc(txreadyq, port, 1);
-+ BUG_ON(n < 0);
-+ desc = tx_desc_ptr(port, n);
-+
-+#ifdef __ARMEB__
-+ port->tx_buff_tab[n] = skb;
-+#else
-+ port->tx_buff_tab[n] = mem;
-+#endif
-+ desc->data = phys + offset;
-+ desc->buf_len = desc->pkt_len = len;
-+
-+ wmb();
-+ queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
-+ dev->trans_start = jiffies;
-+
-+ if (qmgr_stat_empty(txreadyq)) {
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
-+#endif
-+ netif_stop_queue(dev);
-+ /* we could miss TX ready interrupt */
-+ if (!qmgr_stat_empty(txreadyq)) {
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
-+ dev->name);
-+#endif
-+ netif_wake_queue(dev);
-+ }
-+ }
-+
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
-+#endif
-+ return NETDEV_TX_OK;
-+}
-+
-+
-+static int request_hdlc_queues(struct port *port)
-+{
-+ int err;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
-+ if (err)
-+ return err;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_rxfree;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_rx;
-+
-+ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_tx;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_txready;
-+ return 0;
-+
-+rel_txready:
-+ qmgr_release_queue(port->plat->txreadyq);
-+rel_tx:
-+ qmgr_release_queue(queue_ids[port->id].tx);
-+rel_rx:
-+ qmgr_release_queue(queue_ids[port->id].rx);
-+rel_rxfree:
-+ qmgr_release_queue(queue_ids[port->id].rxfree);
-+ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
-+ port->netdev->name);
-+ return err;
-+}
-+
-+static void release_hdlc_queues(struct port *port)
-+{
-+ qmgr_release_queue(queue_ids[port->id].rxfree);
-+ qmgr_release_queue(queue_ids[port->id].rx);
-+ qmgr_release_queue(queue_ids[port->id].txdone);
-+ qmgr_release_queue(queue_ids[port->id].tx);
-+ qmgr_release_queue(port->plat->txreadyq);
-+}
-+
-+static int init_hdlc_queues(struct port *port)
-+{
-+ int i;
-+
-+ if (!ports_open)
-+ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
-+ POOL_ALLOC_SIZE, 32, 0)))
-+ return -ENOMEM;
-+
-+ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
-+ &port->desc_tab_phys)))
-+ return -ENOMEM;
-+ memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
-+ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
-+ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
-+
-+ /* Setup RX buffers */
-+ for (i = 0; i < RX_DESCS; i++) {
-+ struct desc *desc = rx_desc_ptr(port, i);
-+ buffer_t *buff;
-+ void *data;
-+#ifdef __ARMEB__
-+ if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
-+ return -ENOMEM;
-+ data = buff->data;
-+#else
-+ if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
-+ return -ENOMEM;
-+ data = buff;
-+#endif
-+ desc->buf_len = RX_SIZE;
-+ desc->data = dma_map_single(&port->netdev->dev, data,
-+ RX_SIZE, DMA_FROM_DEVICE);
-+ if (dma_mapping_error(desc->data)) {
-+ free_buffer(buff);
-+ return -EIO;
-+ }
-+ port->rx_buff_tab[i] = buff;
-+ }
-+
-+ return 0;
-+}
-+
-+static void destroy_hdlc_queues(struct port *port)
-+{
-+ int i;
-+
-+ if (port->desc_tab) {
-+ for (i = 0; i < RX_DESCS; i++) {
-+ struct desc *desc = rx_desc_ptr(port, i);
-+ buffer_t *buff = port->rx_buff_tab[i];
-+ if (buff) {
-+ dma_unmap_single(&port->netdev->dev,
-+ desc->data, RX_SIZE,
-+ DMA_FROM_DEVICE);
-+ free_buffer(buff);
-+ }
-+ }
-+ for (i = 0; i < TX_DESCS; i++) {
-+ struct desc *desc = tx_desc_ptr(port, i);
-+ buffer_t *buff = port->tx_buff_tab[i];
-+ if (buff) {
-+ dma_unmap_tx(port, desc);
-+ free_buffer(buff);
-+ }
-+ }
-+ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
-+ port->desc_tab = NULL;
-+ }
-+
-+ if (!ports_open && dma_pool) {
-+ dma_pool_destroy(dma_pool);
-+ dma_pool = NULL;
-+ }
-+}
-+
-+static int hss_hdlc_open(struct net_device *dev)
-+{
-+ struct port *port = dev_to_port(dev);
-+ unsigned long flags;
-+ int i, err = 0;
-+
-+ if ((err = hdlc_open(dev)))
-+ return err;
-+
-+ if ((err = request_hdlc_queues(port)))
-+ goto err_hdlc_close;
-+
-+ if ((err = init_hdlc_queues(port)))
-+ goto err_destroy_queues;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
-+ err = -EBUSY; /* channel #0 is used for G.704 framing */
-+ goto err_unlock;
-+ }
-+ if (port->mode != MODE_HDLC)
-+ for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
-+ if (port->channels[i] == CHANNEL_HDLC) {
-+ err = -ECHRNG; /* frame too short */
-+ goto err_unlock;
-+ }
-+
-+ if ((err = hss_config_load_firmware(port)))
-+ goto err_unlock;
-+
-+ if (!port->chan_open_count && port->plat->open)
-+ if ((err = port->plat->open(port->id, dev,
-+ hss_hdlc_set_carrier)))
-+ goto err_unlock;
-+
-+ if (port->mode == MODE_G704 && !port->chan_open_count)
-+ if ((err = hss_prepare_chan(port)))
-+ goto err_plat_close;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ /* Populate queues with buffers, no failure after this point */
-+ for (i = 0; i < TX_DESCS; i++)
-+ queue_put_desc(port->plat->txreadyq,
-+ tx_desc_phys(port, i), tx_desc_ptr(port, i));
-+
-+ for (i = 0; i < RX_DESCS; i++)
-+ queue_put_desc(queue_ids[port->id].rxfree,
-+ rx_desc_phys(port, i), rx_desc_ptr(port, i));
-+
-+ napi_enable(&port->napi);
-+ netif_start_queue(dev);
-+
-+ qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
-+ hss_hdlc_rx_irq, dev);
-+
-+ qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
-+ hss_hdlc_txdone_irq, dev);
-+ qmgr_enable_irq(queue_ids[port->id].txdone);
-+
-+ ports_open++;
-+ port->hdlc_open = 1;
-+
-+ hss_config_set_hdlc_cfg(port);
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+
-+ if (port->mode == MODE_G704 && !port->chan_open_count)
-+ hss_config_start_chan(port);
-+
-+ hss_config_start_hdlc(port);
-+
-+ /* we may already have RX data, enables IRQ */
-+ netif_rx_schedule(dev, &port->napi);
-+ return 0;
-+
-+err_plat_close:
-+ if (!port->chan_open_count && port->plat->close)
-+ port->plat->close(port->id, dev);
-+err_unlock:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+err_destroy_queues:
-+ destroy_hdlc_queues(port);
-+ release_hdlc_queues(port);
-+err_hdlc_close:
-+ hdlc_close(dev);
-+ return err;
-+}
-+
-+static int hss_hdlc_close(struct net_device *dev)
-+{
-+ struct port *port = dev_to_port(dev);
-+ unsigned long flags;
-+ int i, buffs = RX_DESCS; /* allocated RX buffers */
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ ports_open--;
-+ port->hdlc_open = 0;
-+ qmgr_disable_irq(queue_ids[port->id].rx);
-+ netif_stop_queue(dev);
-+ napi_disable(&port->napi);
-+
-+ hss_config_stop_hdlc(port);
-+
-+ if (port->mode == MODE_G704 && !port->chan_open_count)
-+ hss_chan_stop(port);
-+
-+ while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
-+ buffs--;
-+ while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
-+ buffs--;
-+
-+ if (buffs)
-+ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
-+ " left in NPE\n", dev->name, buffs);
-+
-+ buffs = TX_DESCS;
-+ while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
-+ buffs--; /* cancel TX */
-+
-+ i = 0;
-+ do {
-+ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
-+ buffs--;
-+ if (!buffs)
-+ break;
-+ } while (++i < MAX_CLOSE_WAIT);
-+
-+ if (buffs)
-+ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
-+ "left in NPE\n", dev->name, buffs);
-+#if DEBUG_CLOSE
-+ if (!buffs)
-+ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
-+#endif
-+ qmgr_disable_irq(queue_ids[port->id].txdone);
-+
-+ if (!port->chan_open_count && port->plat->close)
-+ port->plat->close(port->id, dev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ destroy_hdlc_queues(port);
-+ release_hdlc_queues(port);
-+ hdlc_close(dev);
-+ return 0;
-+}
-+
-+
-+static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
-+ unsigned short parity)
-+{
-+ struct port *port = dev_to_port(dev);
-+
-+ if (encoding != ENCODING_NRZ)
-+ return -EINVAL;
-+
-+ switch(parity) {
-+ case PARITY_CRC16_PR1_CCITT:
-+ port->hdlc_cfg = 0;
-+ return 0;
-+
-+ case PARITY_CRC32_PR1_CCITT:
-+ port->hdlc_cfg = PKT_HDLC_CRC_32;
-+ return 0;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+
-+static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
-+{
-+ const size_t size = sizeof(sync_serial_settings);
-+ sync_serial_settings new_line;
-+ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
-+ struct port *port = dev_to_port(dev);
-+ unsigned long flags;
-+ int i, clk;
-+
-+ if (cmd != SIOCWANDEV)
-+ return hdlc_ioctl(dev, ifr, cmd);
-+
-+ switch(ifr->ifr_settings.type) {
-+ case IF_GET_IFACE:
-+ ifr->ifr_settings.type = IF_IFACE_V35;
-+ if (ifr->ifr_settings.size < size) {
-+ ifr->ifr_settings.size = size; /* data size wanted */
-+ return -ENOBUFS;
-+ }
-+ memset(&new_line, 0, sizeof(new_line));
-+ new_line.clock_type = port->clock_type;
-+ new_line.clock_rate = port->clock_rate;
-+ new_line.loopback = port->loopback;
-+ if (copy_to_user(line, &new_line, size))
-+ return -EFAULT;
-+
-+ if (!port->chan_buf)
-+ return 0;
-+
-+ dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
-+ chan_rx_buf_len(port), DMA_FROM_DEVICE);
-+ printk(KERN_DEBUG "RX:\n");
-+ for (i = 0; i < chan_rx_buf_len(port); i++) {
-+ if (i % 32 == 0)
-+ printk(KERN_DEBUG "%03X ", i);
-+ printk("%02X%c", chan_rx_buf(port)[i],
-+ (i + 1) % 32 ? ' ' : '\n');
-+ }
-+
-+#if 0
-+ printk(KERN_DEBUG "TX:\n");
-+ for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
-+ + chan_tx_lists_len(port); i++) {
-+ if (i % 32 == 0)
-+ printk(KERN_DEBUG "%03X ", i);
-+ printk("%02X%c", chan_tx_buf(port)[i],
-+ (i + 1) % 32 ? ' ' : '\n');
-+ }
-+#endif
-+ port->msg_count = 10;
-+ return 0;
-+
-+ case IF_IFACE_SYNC_SERIAL:
-+ case IF_IFACE_V35:
-+ if(!capable(CAP_NET_ADMIN))
-+ return -EPERM;
-+ if (copy_from_user(&new_line, line, size))
-+ return -EFAULT;
-+
-+ clk = new_line.clock_type;
-+ if (port->plat->set_clock)
-+ clk = port->plat->set_clock(port->id, clk);
-+
-+ if (clk != CLOCK_EXT && clk != CLOCK_INT)
-+ return -EINVAL; /* No such clock setting */
-+
-+ if (new_line.loopback != 0 && new_line.loopback != 1)
-+ return -EINVAL;
-+
-+ port->clock_type = clk; /* Update settings */
-+ /* FIXME port->clock_rate = new_line.clock_rate */;
-+ port->loopback = new_line.loopback;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_line(port);
-+ hss_config_load(port);
-+ }
-+ if (port->loopback || port->carrier)
-+ netif_carrier_on(port->netdev);
-+ else
-+ netif_carrier_off(port->netdev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ return 0;
-+
-+ default:
-+ return hdlc_ioctl(dev, ifr, cmd);
-+ }
-+}
-+
-+/*****************************************************************************
-+ * channelized (G.704) operation
-+ ****************************************************************************/
-+
-+static void g704_rx_framer(struct port *port, unsigned int offset)
-+{
-+ u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
-+ CHAN_RX_FRAMES);
-+ unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
-+ unsigned int is_first = port->just_set_offset;
-+ u8 zeros_even, zeros_odd, ones_even, ones_odd;
-+ enum alignment aligned;
-+
-+ port->just_set_offset = 0;
-+ dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
-+ DMA_FROM_DEVICE);
-+
-+ /* check if aligned first */
-+ for (frame = 0; frame < CHAN_RX_TRIGGER &&
-+ (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
-+ bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
-+ u8 ve = data[frame];
-+ u8 vo = data[frame + 1];
-+
-+ if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
-+ bad_even++;
-+
-+ if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
-+ bad_odd++;
-+ }
-+
-+ if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
-+ aligned = EVEN_FIRST;
-+ else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
-+ aligned = ODD_FIRST;
-+ else
-+ aligned = NOT_ALIGNED;
-+
-+ if (aligned != NOT_ALIGNED) {
-+ if (aligned == port->aligned)
-+ return; /* no change */
-+ if (printk_ratelimit())
-+ printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
-+ " first)\n", port->id, port->frame_sync_offset,
-+ aligned == EVEN_FIRST ? "even" : "odd");
-+ port->aligned = aligned;
-+
-+ atomic_inc(&port->chan_tx_irq_number);
-+ wake_up_interruptible(&port->chan_tx_waitq);
-+ atomic_inc(&port->chan_rx_irq_number);
-+ wake_up_interruptible(&port->chan_rx_waitq);
-+ return;
-+ }
-+
-+ /* not aligned */
-+ if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
-+ printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
-+ port->aligned = NOT_ALIGNED;
-+#if DEBUG_FRAMER
-+ for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
-+ printk("%c%02X%s", cnt == offset ? '>' : ' ',
-+ chan_rx_buf(port)[cnt],
-+ (cnt + 1) % 32 ? "" : "\n");
-+#endif
-+
-+ for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
-+ if (port->chan_devices[cnt]) {
-+ set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
-+ ->errors_bitmap);
-+ set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
-+ ->errors_bitmap);
-+ }
-+ atomic_inc(&port->chan_tx_irq_number);
-+ wake_up_interruptible(&port->chan_tx_waitq);
-+ atomic_inc(&port->chan_rx_irq_number);
-+ wake_up_interruptible(&port->chan_rx_waitq);
-+ }
-+
-+ if (is_first)
-+ return;
-+
-+ zeros_even = zeros_odd = 0;
-+ ones_even = ones_odd = 0xFF;
-+ for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
-+ zeros_even |= data[frame];
-+ zeros_odd |= data[frame + 1];
-+ ones_even &= data[frame];
-+ ones_odd &= data[frame + 1];
-+ }
-+
-+ for (bit = 0; bit < 7; bit++) {
-+ if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
-+ (ones_odd & 0x40) == 0x40) {
-+ aligned = EVEN_FIRST; /* maybe */
-+ break;
-+ }
-+ if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
-+ (ones_even & 0x40) == 0x40) {
-+ aligned = ODD_FIRST; /* maybe */
-+ break;
-+ }
-+ zeros_even <<= 1;
-+ ones_even = ones_even << 1 | 1;
-+ zeros_odd <<= 1;
-+ ones_odd = ones_odd << 1 | 1;
-+ }
-+
-+ port->frame_sync_offset += port->frame_size - bit;
-+ port->frame_sync_offset %= port->frame_size;
-+ port->just_set_offset = 1;
-+
-+#if DEBUG_FRAMER
-+ if (bit == 7)
-+ printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
-+ port->id, port->frame_sync_offset);
-+ else
-+ printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
-+ " %u (%s frame first)\n", port->id,
-+ port->frame_sync_offset,
-+ aligned == EVEN_FIRST ? "even" : "odd");
-+#endif
-+
-+ hss_config_set_rx_frame(port);
-+ hss_config_load(port);
-+}
-+
-+static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
-+{
-+ /* in bytes */
-+ unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
-+ unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
-+ int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
-+
-+ offset *= list_len;
-+ eaten = sub_offset(offset, last_offset, buff_len);
-+
-+ if (chan_dev->tx_count > eaten + 2 * list_len) {
-+ /* two pages must be reserved for the transmitter */
-+ chan_dev->tx_first += eaten;
-+ chan_dev->tx_first %= buff_len;
-+ chan_dev->tx_count -= eaten;
-+ } else {
-+ /* FIXME check
-+ 0
-+ 1 tx_first (may still be transmited)
-+ 2 tx_offset (currently reported by the NPE)
-+ 3 tx_first + 2 * list_len (free to write here)
-+ 4
-+ 5
-+ */
-+
-+ /* printk(KERN_DEBUG "TX buffer underflow\n"); */
-+ chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
-+ chan_dev->tx_count = 2 * list_len; /* reserve */
-+ set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
-+ }
-+}
-+
-+static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
-+{
-+ /* in bytes */
-+ unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
-+ unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
-+ int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
-+
-+ offset *= chan_dev->chan_count;
-+ chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
-+ buff_len) + trig_len;
-+ if (chan_dev->rx_count > buff_len - 2 * trig_len) {
-+ /* two pages - offset[0] and offset[1] are lost - FIXME check */
-+ /* printk(KERN_DEBUG "RX buffer overflow\n"); */
-+ chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
-+ chan_dev->rx_count = buff_len - 2 * trig_len;
-+ set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
-+ }
-+}
-+
-+static void hss_chan_irq(void *pdev)
-+{
-+ struct port *port = pdev;
-+ u32 v;
-+
-+#if DEBUG_RX
-+ printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
-+#endif
-+ spin_lock(&npe_lock);
-+ while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
-+ unsigned int first, errors, tx_list, rx_frame;
-+ int i, bad;
-+
-+ first = v >> 24;
-+ errors = (v >> 16) & 0xFF;
-+ tx_list = (v >> 8) & 0xFF;
-+ rx_frame = v & 0xFF;
-+
-+ if (port->msg_count) {
-+ printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
-+ " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
-+ " 0x%02X\n", port->id, jiffies, first, errors,
-+ tx_list, rx_frame);
-+ port->msg_count--;
-+ }
-+
-+ BUG_ON(rx_frame % CHAN_RX_TRIGGER);
-+ BUG_ON(rx_frame >= CHAN_RX_FRAMES);
-+ BUG_ON(tx_list >= CHAN_TX_LISTS);
-+
-+ bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
-+ if (!bad && tx_list != port->chan_last_tx) {
-+ if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
-+ printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
-+ " current %i\n", port->chan_last_tx,
-+ tx_list);
-+ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
-+ if (!port->chan_devices[i] ||
-+ !port->chan_devices[i]->open_count)
-+ continue;
-+ chan_process_tx_irq(port->chan_devices[i],
-+ tx_list);
-+ }
-+ atomic_inc(&port->chan_tx_irq_number);
-+#if 0
-+ printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
-+ jiffies, errors);
-+#endif
-+ wake_up_interruptible(&port->chan_tx_waitq);
-+ }
-+
-+ if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
-+ CHAN_RX_FRAMES)
-+ printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
-+ " current %i\n", port->chan_last_rx, rx_frame);
-+
-+ if (port->mode == MODE_G704)
-+ g704_rx_framer(port, rx_frame);
-+
-+ if (!bad &&
-+ (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
-+ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
-+ if (!port->chan_devices[i] ||
-+ !port->chan_devices[i]->open_count)
-+ continue;
-+ chan_process_rx_irq(port->chan_devices[i],
-+ rx_frame);
-+ }
-+ atomic_inc(&port->chan_rx_irq_number);
-+ wake_up_interruptible(&port->chan_rx_waitq);
-+ }
-+ port->chan_last_tx = tx_list;
-+ port->chan_last_rx = rx_frame;
-+ }
-+ spin_unlock(&npe_lock);
-+}
-+
-+
-+static int hss_prepare_chan(struct port *port)
-+{
-+ int err;
-+
-+ if ((err = hss_config_load_firmware(port)))
-+ return err;
-+
-+ if ((err = qmgr_request_queue(queue_ids[port->id].chan,
-+ CHAN_QUEUE_LEN, 0, 0)))
-+ return err;
-+
-+ if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
-+ chan_tx_lists_len(port) +
-+ chan_rx_buf_len(port), GFP_KERNEL))) {
-+ goto release_queue;
-+ err = -ENOBUFS;
-+ }
-+
-+ port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
-+ chan_tx_buf_len(port) +
-+ chan_tx_lists_len(port),
-+ DMA_TO_DEVICE);
-+ if (dma_mapping_error(port->chan_tx_buf_phys)) {
-+ err = -EIO;
-+ goto free;
-+ }
-+
-+ port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
-+ chan_rx_buf_len(port),
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(port->chan_rx_buf_phys)) {
-+ err = -EIO;
-+ goto unmap_tx;
-+ }
-+
-+ qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
-+ hss_chan_irq, port);
-+ qmgr_enable_irq(queue_ids[port->id].chan);
-+ hss_chan_irq(port);
-+ return 0;
-+
-+unmap_tx:
-+ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port) + chan_tx_lists_len(port),
-+ DMA_TO_DEVICE);
-+free:
-+ kfree(port->chan_buf);
-+ port->chan_buf = NULL;
-+release_queue:
-+ qmgr_release_queue(queue_ids[port->id].chan);
-+ return err;
-+}
-+
-+void hss_chan_stop(struct port *port)
-+{
-+ if (!port->chan_open_count && !port->hdlc_open)
-+ qmgr_disable_irq(queue_ids[port->id].chan);
-+
-+ hss_config_stop_chan(port);
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+
-+ if (!port->chan_open_count && !port->hdlc_open) {
-+ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port) +
-+ chan_tx_lists_len(port), DMA_TO_DEVICE);
-+ dma_unmap_single(port->dev, port->chan_rx_buf_phys,
-+ chan_rx_buf_len(port), DMA_FROM_DEVICE);
-+ kfree(port->chan_buf);
-+ port->chan_buf = NULL;
-+ qmgr_release_queue(queue_ids[port->id].chan);
-+ }
-+}
-+
-+static int hss_chan_open(struct inode *inode, struct file *file)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev(inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ int i, err = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (chan_dev->open_count) {
-+ if (chan_dev->excl_open || (file->f_flags & O_EXCL))
-+ err = -EBUSY;
-+ else
-+ chan_dev->open_count++;
-+ goto out;
-+ }
-+
-+ if (port->mode == MODE_HDLC) {
-+ err = -ENOSYS;
-+ goto out;
-+ }
-+
-+ if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
-+ err = -EBUSY; /* channel #0 is used for G.704 signaling */
-+ goto out;
-+ }
-+ for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
-+ if (port->channels[i - 1] == chan_dev->id) {
-+ err = -ECHRNG; /* frame too short */
-+ goto out;
-+ }
-+
-+ chan_dev->rx_first = chan_dev->tx_first = 0;
-+ chan_dev->rx_count = chan_dev->tx_count = 0;
-+ clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
-+ clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
-+
-+ if (!port->chan_open_count && !port->hdlc_open) {
-+ if (port->plat->open)
-+ if ((err = port->plat->open(port->id, port->netdev,
-+ hss_hdlc_set_carrier)))
-+ goto out;
-+ if ((err = hss_prepare_chan(port))) {
-+ if (port->plat->close)
-+ port->plat->close(port->id, port->netdev);
-+ goto out;
-+ }
-+ }
-+
-+ hss_config_stop_chan(port);
-+ chan_dev->open_count++;
-+ port->chan_open_count++;
-+ chan_dev->excl_open = !!file->f_flags & O_EXCL;
-+
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+ hss_config_start_chan(port);
-+out:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static int hss_chan_release(struct inode *inode, struct file *file)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev(inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (!--chan_dev->open_count) {
-+ if (!--port->chan_open_count && !port->hdlc_open) {
-+ hss_chan_stop(port);
-+ if (port->plat->close)
-+ port->plat->close(port->id, port->netdev);
-+ } else {
-+ hss_config_stop_chan(port);
-+ hss_config_set_lut(port);
-+ hss_config_set_line(port); //
-+ hss_config_start_chan(port);
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return 0;
-+}
-+
-+static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
-+ loff_t *f_pos)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev
-+ (file->f_path.dentry->d_inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ u8 *rx_buf;
-+ int res = 0, loops = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ while (1) {
-+ int prev_irq = atomic_read(&port->chan_rx_irq_number);
-+#if 0
-+ if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
-+ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
-+ res = -EIO;
-+ goto out;
-+ }
-+#endif
-+ if (count == 0)
-+ goto out; /* no need to wait */
-+
-+ if (chan_dev->rx_count)
-+ break;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ loops++;
-+ if ((res = wait_event_interruptible
-+ (port->chan_rx_waitq,
-+ atomic_read(&port->chan_rx_irq_number) != prev_irq)))
-+ goto out;
-+ spin_lock_irqsave(&npe_lock, flags);
-+ continue;
-+ }
-+
-+ dma_sync_single(port->dev, port->chan_rx_buf_phys,
-+ chan_rx_buf_len(port), DMA_FROM_DEVICE);
-+
-+#if 0
-+ if (loops > 1)
-+ printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
-+ " last_rx %u loops %i\n", chan_dev->rx_first,
-+ chan_dev->rx_count, count, port->chan_last_rx, loops);
-+#endif
-+ rx_buf = chan_rx_buf(port);
-+ while (chan_dev->rx_count > 0 && res < count) {
-+ unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
-+ unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
-+
-+ chan = chan_dev->log_channels[chan];
-+ if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
-+ res = -EFAULT;
-+ goto out;
-+ }
-+ chan_dev->rx_first++;
-+ chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
-+ chan_dev->rx_count--;
-+ res++;
-+ }
-+out:
-+#if 0
-+ printk(KERN_DEBUG "EXIT rx_first %u rx_count %u res %i\n",
-+ chan_dev->rx_first, chan_dev->rx_count, res);
-+#endif
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return res;
-+}
-+
-+static ssize_t hss_chan_write(struct file *file, const char __user *buf,
-+ size_t count, loff_t *f_pos)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev
-+ (file->f_path.dentry->d_inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ u8 *tx_buf;
-+ int res = 0, loops = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ while (1) {
-+ int prev_irq = atomic_read(&port->chan_tx_irq_number);
-+#if 0
-+ if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
-+ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
-+ res = -EIO;
-+ goto out;
-+ }
-+#endif
-+ if (count == 0)
-+ goto out; /* no need to wait */
-+
-+ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
-+ break;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ loops++;
-+ if ((res = wait_event_interruptible
-+ (port->chan_tx_waitq,
-+ atomic_read (&port->chan_tx_irq_number) != prev_irq)))
-+ goto out;
-+ spin_lock_irqsave(&npe_lock, flags);
-+ continue;
-+ }
-+
-+#if 0
-+ if (loops > 1)
-+ printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
-+ " last_tx %u loops %i\n", chan_dev->tx_first,
-+ chan_dev->tx_count, count, port->chan_last_tx, loops);
-+#endif
-+ tx_buf = chan_tx_buf(port);
-+ while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
-+ res < count) {
-+ unsigned int tail, chan, frame;
-+
-+ tail = (chan_dev->tx_first + chan_dev->tx_count) %
-+ (CHAN_TX_FRAMES * chan_dev->chan_count);
-+ chan = tail % chan_dev->chan_count;
-+ frame = tail / chan_dev->chan_count;
-+ chan = chan_dev->log_channels[chan];
-+
-+ if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
-+ printk(KERN_DEBUG "BUG? TX %u %u %u\n",
-+ tail, chan, frame);
-+ res = -EFAULT;
-+ goto out_sync;
-+ }
-+ chan_dev->tx_count++;
-+ res++;
-+ }
-+out_sync:
-+ dma_sync_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port), DMA_TO_DEVICE);
-+out:
-+#if 0
-+ printk(KERN_DEBUG "EXIT TX_first %u tx_count %u res %i\n",
-+ chan_dev->tx_first, chan_dev->tx_count, res);
-+#endif
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return res;
-+}
-+
-+
-+static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev
-+ (file->f_path.dentry->d_inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ unsigned int mask = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ poll_wait(file, &port->chan_tx_waitq, wait);
-+ poll_wait(file, &port->chan_rx_waitq, wait);
-+
-+ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
-+ mask |= POLLOUT | POLLWRNORM;
-+ if (chan_dev->rx_count)
-+ mask |= POLLIN | POLLRDNORM;
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return mask;
-+}
-+
-+/*****************************************************************************
-+ * channelized device sysfs attributes
-+ ****************************************************************************/
-+
-+static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct chan_device *chan_dev = dev_get_drvdata(dev);
-+
-+ return print_channels(chan_dev->port, buf, chan_dev->id);
-+}
-+
-+static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct chan_device *chan_dev = dev_get_drvdata(dev);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ unsigned int ch;
-+ size_t orig_len = len;
-+ int err;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (len != 7 || memcmp(buf, "destroy", 7))
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ cdev_del(&chan_dev->cdev);
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (port->channels[ch] == chan_dev->id)
-+ port->channels[ch] = CHANNEL_UNUSED;
-+ port->chan_devices[chan_dev->id] = NULL;
-+ kfree(chan_dev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ if ((err = device_schedule_callback(dev, device_unregister)))
-+ return err;
-+ return orig_len;
-+}
-+
-+static struct device_attribute chan_attr =
-+ __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
-+
-+/*****************************************************************************
-+ * main sysfs attributes
-+ ****************************************************************************/
-+
-+static const struct file_operations chan_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .read = hss_chan_read,
-+ .write = hss_chan_write,
-+ .poll = hss_chan_poll,
-+ .open = hss_chan_open,
-+ .release = hss_chan_release,
-+};
-+
-+static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ struct chan_device *chan_dev;
-+ u8 channels[MAX_CHANNELS];
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int ch, id;
-+ int minor, err;
-+
-+ if ((err = parse_channels(&buf, &len, channels)) < 1)
-+ return err;
-+
-+ if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
-+ return -ENOBUFS;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
-+ err = -EINVAL;
-+ goto free;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
-+ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
-+ err = -EBUSY;
-+ goto free;
-+ }
-+
-+ for (id = 0; id < MAX_CHAN_DEVICES; id++)
-+ if (port->chan_devices[id] == NULL)
-+ break;
-+
-+ if (id == MAX_CHAN_DEVICES) {
-+ err = -EBUSY;
-+ goto free;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch])
-+ break;
-+
-+ minor = port->id * MAX_CHAN_DEVICES + ch;
-+ chan_dev->id = id;
-+ chan_dev->port = port;
-+ chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
-+ "hss%uch%u", port->id, ch);
-+ if (IS_ERR(chan_dev->dev)) {
-+ err = PTR_ERR(chan_dev->dev);
-+ goto free;
-+ }
-+
-+ cdev_init(&chan_dev->cdev, &chan_fops);
-+ chan_dev->cdev.owner = THIS_MODULE;
-+ if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
-+ goto destroy_device;
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch])
-+ port->channels[ch] = id;
-+ port->chan_devices[id] = chan_dev;
-+ dev_set_drvdata(chan_dev->dev, chan_dev);
-+ BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+
-+destroy_device:
-+ device_unregister(chan_dev->dev);
-+free:
-+ kfree(chan_dev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
-+}
-+
-+static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ u8 channels[MAX_CHANNELS];
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int ch;
-+ int err;
-+
-+ if ((err = parse_channels(&buf, &len, channels)) < 0)
-+ return err;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
-+ err = -EINVAL;
-+ goto err;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch] &&
-+ port->channels[ch] != CHANNEL_UNUSED &&
-+ port->channels[ch] != CHANNEL_HDLC) {
-+ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
-+ err = -EBUSY;
-+ goto err;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch])
-+ port->channels[ch] = CHANNEL_HDLC;
-+ else if (port->channels[ch] == CHANNEL_HDLC)
-+ port->channels[ch] = CHANNEL_UNUSED;
-+
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+
-+err:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static ssize_t show_clock_type(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
-+ return 5;
-+}
-+
-+static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int clk, err;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (len != 3)
-+ return -EINVAL;
-+ if (!memcmp(buf, "ext", 3))
-+ clk = CLOCK_EXT;
-+ else if (!memcmp(buf, "int", 3))
-+ clk = CLOCK_INT;
-+ else
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ if (port->plat->set_clock)
-+ clk = port->plat->set_clock(port->id, clk);
-+ if (clk != CLOCK_EXT && clk != CLOCK_INT) {
-+ err = -EINVAL; /* plat->set_clock shouldn't change the state */
-+ goto err;
-+ }
-+ port->clock_type = clk;
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_line(port);
-+ hss_config_load(port);
-+ }
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ return orig_len;
-+err:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static ssize_t show_clock_rate(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ sprintf(buf, "%u\n", port->clock_rate);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+#if 0
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int rate;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
-+ return -EINVAL;
-+ if (len)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ port->clock_rate = rate;
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+#endif
-+ return -EINVAL; /* FIXME not yet supported */
-+}
-+
-+static ssize_t show_frame_size(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704)
-+ return -EINVAL;
-+
-+ sprintf(buf, "%u\n", port->frame_size);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t ret = len;
-+ unsigned long flags;
-+ unsigned int size;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
-+ return -EINVAL;
-+ if (len || size % 8 > 1)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704)
-+ ret = -EINVAL;
-+ else if (!port->chan_open_count && !port->hdlc_open)
-+ ret = -EBUSY;
-+ else {
-+ port->frame_size = size;
-+ port->frame_sync_offset = 0;
-+ }
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return ret;
-+}
-+
-+static ssize_t show_frame_offset(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ sprintf(buf, "%u\n", port->frame_sync_offset);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_frame_offset(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int offset;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
-+ return -EINVAL;
-+ if (len)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ port->frame_sync_offset = offset;
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_rx_frame(port);
-+ hss_config_load(port);
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+}
-+
-+static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ sprintf(buf, "%u\n", port->loopback);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int lb;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &lb, 0, 1))
-+ return -EINVAL;
-+ if (len)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->loopback != lb) {
-+ port->loopback = lb;
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_core(port);
-+ hss_config_load(port);
-+ }
-+ if (port->loopback || port->carrier)
-+ netif_carrier_on(port->netdev);
-+ else
-+ netif_carrier_off(port->netdev);
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+}
-+
-+static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ switch(port->mode) {
-+ case MODE_RAW:
-+ strcpy(buf, "raw\n");
-+ break;
-+ case MODE_G704:
-+ strcpy(buf, "g704\n");
-+ break;
-+ default:
-+ strcpy(buf, "hdlc\n");
-+ break;
-+ }
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t ret = len;
-+ unsigned long flags;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->chan_open_count || port->hdlc_open) {
-+ ret = -EBUSY;
-+ } else if (len == 4 && !memcmp(buf, "hdlc", 4))
-+ port->mode = MODE_HDLC;
-+ else if (len == 3 && !memcmp(buf, "raw", 3))
-+ port->mode = MODE_RAW;
-+ else if (len == 4 && !memcmp(buf, "g704", 4))
-+ port->mode = MODE_G704;
-+ else
-+ ret = -EINVAL;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return ret;
-+}
-+
-+static struct device_attribute hss_attrs[] = {
-+ __ATTR(create_chan, 0200, NULL, create_chan),
-+ __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
-+ __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
-+ __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
-+ __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
-+ __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
-+ __ATTR(loopback, 0644, show_loopback, set_loopback),
-+ __ATTR(mode, 0644, show_mode, set_mode),
-+};
-+
-+/*****************************************************************************
-+ * initialization
-+ ****************************************************************************/
-+
-+static int __devinit hss_init_one(struct platform_device *pdev)
-+{
-+ struct port *port;
-+ struct net_device *dev;
-+ hdlc_device *hdlc;
-+ int i, err;
-+
-+ if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
-+ return -ENOMEM;
-+ platform_set_drvdata(pdev, port);
-+ port->id = pdev->id;
-+
-+ if ((port->npe = npe_request(0)) == NULL) {
-+ err = -ENOSYS;
-+ goto err_free;
-+ }
-+
-+ port->dev = &pdev->dev;
-+ port->plat = pdev->dev.platform_data;
-+ if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
-+ err = -ENOMEM;
-+ goto err_plat;
-+ }
-+
-+ SET_NETDEV_DEV(dev, &pdev->dev);
-+ hdlc = dev_to_hdlc(dev);
-+ hdlc->attach = hss_hdlc_attach;
-+ hdlc->xmit = hss_hdlc_xmit;
-+ dev->open = hss_hdlc_open;
-+ dev->stop = hss_hdlc_close;
-+ dev->do_ioctl = hss_hdlc_ioctl;
-+ dev->tx_queue_len = 100;
-+ port->clock_type = CLOCK_EXT;
-+ port->clock_rate = 2048000;
-+ port->frame_size = 256; /* E1 */
-+ memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
-+ init_waitqueue_head(&port->chan_tx_waitq);
-+ init_waitqueue_head(&port->chan_rx_waitq);
-+ netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
-+
-+ if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
-+ goto err_free_netdev;
-+
-+ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
-+ BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
-+
-+ printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
-+ return 0;
-+
-+err_free_netdev:
-+ free_netdev(dev);
-+err_plat:
-+ npe_release(port->npe);
-+ platform_set_drvdata(pdev, NULL);
-+err_free:
-+ kfree(port);
-+ return err;
-+}
-+
-+static int __devexit hss_remove_one(struct platform_device *pdev)
-+{
-+ struct port *port = platform_get_drvdata(pdev);
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
-+ device_remove_file(port->dev, &hss_attrs[i]);
-+
-+ unregister_hdlc_device(port->netdev);
-+ free_netdev(port->netdev);
-+ npe_release(port->npe);
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(port);
-+ return 0;
-+}
-+
-+static struct platform_driver drv = {
-+ .driver.name = DRV_NAME,
-+ .probe = hss_init_one,
-+ .remove = hss_remove_one,
-+};
-+
-+static int __init hss_init_module(void)
-+{
-+ int err;
-+ dev_t rdev;
-+
-+ if ((ixp4xx_read_feature_bits() &
-+ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
-+ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
-+ return -ENOSYS;
-+
-+ if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
-+ "hss")))
-+ return err;
-+
-+ spin_lock_init(&npe_lock);
-+
-+ if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
-+ printk(KERN_ERR "Can't register device class 'hss'\n");
-+ err = PTR_ERR(hss_class);
-+ goto free_chrdev;
-+ }
-+ if ((err = platform_driver_register(&drv)))
-+ goto destroy_class;
-+
-+ chan_major = MAJOR(rdev);
-+ return 0;
-+
-+destroy_class:
-+ class_destroy(hss_class);
-+free_chrdev:
-+ unregister_chrdev_region(MKDEV(chan_major, 0),
-+ HSS_COUNT * MAX_CHAN_DEVICES);
-+ return err;
-+}
-+
-+static void __exit hss_cleanup_module(void)
-+{
-+ platform_driver_unregister(&drv);
-+ class_destroy(hss_class);
-+ unregister_chrdev_region(MKDEV(chan_major, 0),
-+ HSS_COUNT * MAX_CHAN_DEVICES);
-+}
-+
-+MODULE_AUTHOR("Krzysztof Halasa");
-+MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:ixp4xx_hss");
-+module_init(hss_init_module);
-+module_exit(hss_cleanup_module);
--- /dev/null
+Index: linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c
+===================================================================
+--- linux-2.6.24.2.orig/drivers/net/arm/ixp4xx_eth.c
++++ linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c
+@@ -322,8 +322,12 @@ static void phy_reset(struct net_device
+ struct port *port = netdev_priv(dev);
+ int phy_id = port->mii[idx].phy_id;
+ int cycles = 0;
++ u16 bmcr;
+
+- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
++ /* reset the PHY */
++ bmcr = mdio_read(dev, phy_id, MII_BMCR);
++ bmcr |= BMCR_ANENABLE;
++ mdio_write(dev, phy_id, MII_BMCR, bmcr | BMCR_RESET);
+
+ while (cycles < MAX_MII_RESET_RETRIES) {
+ if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
+@@ -331,13 +335,23 @@ static void phy_reset(struct net_device
+ printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
+ dev->name, cycles);
+ #endif
+- return;
++ break;
+ }
+ udelay(1);
+ cycles++;
+ }
+
+- printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
++ if (cycles == MAX_MII_RESET_RETRIES) {
++ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name,
++ phy_id);
++ return;
++ }
++
++ /* restart auto negotiation */
++ bmcr = mdio_read(dev, phy_id, MII_BMCR);
++ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
++ mdio_write(dev, phy_id, MII_BMCR, bmcr);
++
+ }
+
+ static void eth_set_duplex(struct port *port, int full_duplex)
--- /dev/null
+diff -Nur linux-2.6.24.2/arch/arm/mach-ixp4xx/ixp4xx_npe.c linux-2.6.24.2-owrt/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+--- linux-2.6.24.2/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2008-04-22 12:24:29.000000000 +0200
++++ linux-2.6.24.2-owrt/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2008-04-24 13:26:56.000000000 +0200
+@@ -571,8 +571,8 @@
+ for (i = 0; i < image->size; i++)
+ image->data[i] = swab32(image->data[i]);
+
+- if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
+- print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
++ if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
++ print_npe(KERN_INFO, npe, "IXP46x/IXP43x firmware ignored on "
+ "IXP42x\n");
+ goto err;
+ }
+@@ -594,7 +594,7 @@
+ "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
+ (image->id >> 8) & 0xFF, image->id & 0xFF);
+
+- if (!cpu_is_ixp46x()) {
++ if (cpu_is_ixp42x()) {
+ if (!npe->id)
+ instr_size = NPE_A_42X_INSTR_SIZE;
+ else
+diff -Nur linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c linux-2.6.24.2-owrt/drivers/net/arm/ixp4xx_eth.c
+--- linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c 2008-04-22 12:24:29.000000000 +0200
++++ linux-2.6.24.2-owrt/drivers/net/arm/ixp4xx_eth.c 2008-04-24 18:23:24.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/kernel.h>
+ #include <linux/mii.h>
+ #include <linux/platform_device.h>
++#include <asm/arch/cpu.h>
+ #include <asm/arch/npe.h>
+ #include <asm/arch/qmgr.h>
+
+@@ -1238,12 +1239,16 @@
+
+ static int __init eth_init_module(void)
+ {
+- if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
+- return -ENOSYS;
+
+- /* All MII PHY accesses use NPE-B Ethernet registers */
+ spin_lock_init(&mdio_lock);
+- mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
++ if (!cpu_is_ixp43x())
++ /* All MII PHY accesses use NPE-B Ethernet registers */
++ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
++
++ else
++ /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
++ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
++
+ __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
+
+ return platform_driver_register(&drv);
+diff -Nur linux-2.6.24.2/include/asm-arm/arch-ixp4xx/cpu.h linux-2.6.24.2-owrt/include/asm-arm/arch-ixp4xx/cpu.h
+--- linux-2.6.24.2/include/asm-arm/arch-ixp4xx/cpu.h 2008-04-22 12:24:29.000000000 +0200
++++ linux-2.6.24.2-owrt/include/asm-arm/arch-ixp4xx/cpu.h 2008-04-24 18:15:29.000000000 +0200
+@@ -34,6 +34,8 @@
+ val &= ~IXP4XX_FEATURE_RESERVED;
+ if (!cpu_is_ixp46x())
+ val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
++ if (cpu_is_ixp42x())
++ val &= ~IXP4XX_FEATURE_IXP43X_46X;
+
+ return val;
+ }
+diff -Nur linux-2.6.24.2/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h linux-2.6.24.2-owrt/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+--- linux-2.6.24.2/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 2008-04-22 12:24:29.000000000 +0200
++++ linux-2.6.24.2-owrt/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 2008-04-24 18:15:13.000000000 +0200
+@@ -628,11 +628,12 @@
+ #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
+ #define IXP4XX_FEATURE_RESERVED (0xFF << 24)
+
+-#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
++#define IXP4XX_FEATURE_IXP43X_46X (IXP4XX_FEATURE_ECC_TIMESYNC | \
+ IXP4XX_FEATURE_USB_HOST | \
+ IXP4XX_FEATURE_NPEA_ETH | \
+- IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
+- IXP4XX_FEATURE_RSA | \
+ IXP4XX_FEATURE_XSCALE_MAX_FREQ)
+
++#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
++ IXP4XX_FEATURE_RSA)
++
+ #endif
--- /dev/null
+diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
+index a3df09e..94e7aa7 100644
+--- a/drivers/net/wan/Kconfig
++++ b/drivers/net/wan/Kconfig
+@@ -334,6 +334,15 @@ config DSCC4_PCI_RST
+
+ Say Y if your card supports this feature.
+
++config IXP4XX_HSS
++ tristate "IXP4xx HSS (synchronous serial port) support"
++ depends on HDLC && ARM && ARCH_IXP4XX
++ select IXP4XX_NPE
++ select IXP4XX_QMGR
++ help
++ Say Y here if you want to use built-in HSS ports
++ on IXP4xx processor.
++
+ config DLCI
+ tristate "Frame Relay DLCI support"
+ ---help---
+diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
+index d61fef3..1b1d116 100644
+--- a/drivers/net/wan/Makefile
++++ b/drivers/net/wan/Makefile
+@@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
+ obj-$(CONFIG_WANXL) += wanxl.o
+ obj-$(CONFIG_PCI200SYN) += pci200syn.o
+ obj-$(CONFIG_PC300TOO) += pc300too.o
++obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
+
+ clean-files := wanxlfw.inc
+ $(obj)/wanxl.o: $(obj)/wanxlfw.inc
+diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
+new file mode 100644
+index 0000000..cf971b3
+--- /dev/null
++++ b/drivers/net/wan/ixp4xx_hss.c
+@@ -0,0 +1,2886 @@
++/*
++ * Intel IXP4xx HSS (synchronous serial port) driver for Linux
++ *
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ */
++
++#include <linux/bitops.h>
++#include <linux/cdev.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/fs.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/hdlc.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <asm/arch/npe.h>
++#include <asm/arch/qmgr.h>
++
++#define DEBUG_QUEUES 0
++#define DEBUG_DESC 0
++#define DEBUG_RX 0
++#define DEBUG_TX 0
++#define DEBUG_PKT_BYTES 0
++#define DEBUG_CLOSE 0
++#define DEBUG_FRAMER 0
++
++#define DRV_NAME "ixp4xx_hss"
++
++#define PKT_EXTRA_FLAGS 0 /* orig 1 */
++#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
++#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
++#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
++
++#define RX_DESCS 16 /* also length of all RX queues */
++#define TX_DESCS 16 /* also length of all TX queues */
++
++#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
++#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
++#define MAX_CLOSE_WAIT 1000 /* microseconds */
++#define HSS_COUNT 2
++#define MIN_FRAME_SIZE 16 /* bits */
++#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
++#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
++#define MAX_CHAN_DEVICES 32
++#define CHANNEL_HDLC 0xFE
++#define CHANNEL_UNUSED 0xFF
++
++#define NAPI_WEIGHT 16
++#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
++#define CHAN_RX_FRAMES 64
++#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
++#define CHAN_TX_LIST_FRAMES 16 /* bytes/channel per list, 16 - 48 */
++#define CHAN_TX_LISTS 8
++#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
++#define CHAN_QUEUE_LEN 16 /* minimum possible */
++
++
++/* Queue IDs */
++#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
++#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
++#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
++#define HSS0_PKT_TX1_QUEUE 15
++#define HSS0_PKT_TX2_QUEUE 16
++#define HSS0_PKT_TX3_QUEUE 17
++#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
++#define HSS0_PKT_RXFREE1_QUEUE 19
++#define HSS0_PKT_RXFREE2_QUEUE 20
++#define HSS0_PKT_RXFREE3_QUEUE 21
++#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
++
++#define HSS1_CHL_RXTRIG_QUEUE 10
++#define HSS1_PKT_RX_QUEUE 0
++#define HSS1_PKT_TX0_QUEUE 5
++#define HSS1_PKT_TX1_QUEUE 6
++#define HSS1_PKT_TX2_QUEUE 7
++#define HSS1_PKT_TX3_QUEUE 8
++#define HSS1_PKT_RXFREE0_QUEUE 1
++#define HSS1_PKT_RXFREE1_QUEUE 2
++#define HSS1_PKT_RXFREE2_QUEUE 3
++#define HSS1_PKT_RXFREE3_QUEUE 4
++#define HSS1_PKT_TXDONE_QUEUE 9
++
++#define NPE_PKT_MODE_HDLC 0
++#define NPE_PKT_MODE_RAW 1
++#define NPE_PKT_MODE_56KMODE 2
++#define NPE_PKT_MODE_56KENDIAN_MSB 4
++
++/* PKT_PIPE_HDLC_CFG_WRITE flags */
++#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
++#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
++#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
++
++
++/* hss_config, PCRs */
++/* Frame sync sampling, default = active low */
++#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
++#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
++#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
++
++/* Frame sync pin: input (default) or output generated off a given clk edge */
++#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
++#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
++
++/* Frame and data clock sampling on edge, default = falling */
++#define PCR_FCLK_EDGE_RISING 0x08000000
++#define PCR_DCLK_EDGE_RISING 0x04000000
++
++/* Clock direction, default = input */
++#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
++
++/* Generate/Receive frame pulses, default = enabled */
++#define PCR_FRM_PULSE_DISABLED 0x01000000
++
++ /* Data rate is full (default) or half the configured clk speed */
++#define PCR_HALF_CLK_RATE 0x00200000
++
++/* Invert data between NPE and HSS FIFOs? (default = no) */
++#define PCR_DATA_POLARITY_INVERT 0x00100000
++
++/* TX/RX endianness, default = LSB */
++#define PCR_MSB_ENDIAN 0x00080000
++
++/* Normal (default) / open drain mode (TX only) */
++#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
++
++/* No framing bit transmitted and expected on RX? (default = framing bit) */
++#define PCR_SOF_NO_FBIT 0x00020000
++
++/* Drive data pins? */
++#define PCR_TX_DATA_ENABLE 0x00010000
++
++/* Voice 56k type: drive the data pins low (default), high, high Z */
++#define PCR_TX_V56K_HIGH 0x00002000
++#define PCR_TX_V56K_HIGH_IMP 0x00004000
++
++/* Unassigned type: drive the data pins low (default), high, high Z */
++#define PCR_TX_UNASS_HIGH 0x00000800
++#define PCR_TX_UNASS_HIGH_IMP 0x00001000
++
++/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
++#define PCR_TX_FB_HIGH_IMP 0x00000400
++
++/* 56k data endiannes - which bit unused: high (default) or low */
++#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
++
++/* 56k data transmission type: 32/8 bit data (default) or 56K data */
++#define PCR_TX_56KS_56K_DATA 0x00000100
++
++/* hss_config, cCR */
++/* Number of packetized clients, default = 1 */
++#define CCR_NPE_HFIFO_2_HDLC 0x04000000
++#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
++
++/* default = no loopback */
++#define CCR_LOOPBACK 0x02000000
++
++/* HSS number, default = 0 (first) */
++#define CCR_SECOND_HSS 0x01000000
++
++
++/* hss_config, clkCR: main:10, num:10, denom:12 */
++#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
++
++#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
++#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
++#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
++#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
++#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
++#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
++
++#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
++#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
++#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
++#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
++#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
++#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
++
++
++/* hss_config, LUT entries */
++#define TDMMAP_UNASSIGNED 0
++#define TDMMAP_HDLC 1 /* HDLC - packetized */
++#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
++#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
++
++/* offsets into HSS config */
++#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
++#define HSS_CONFIG_RX_PCR 0x04
++#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
++#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
++#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
++#define HSS_CONFIG_RX_FCR 0x14
++#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
++#define HSS_CONFIG_RX_LUT 0x38
++
++
++/* NPE command codes */
++/* writes the ConfigWord value to the location specified by offset */
++#define PORT_CONFIG_WRITE 0x40
++
++/* triggers the NPE to load the contents of the configuration table */
++#define PORT_CONFIG_LOAD 0x41
++
++/* triggers the NPE to return an HssErrorReadResponse message */
++#define PORT_ERROR_READ 0x42
++
++/* reset NPE internal status and enable the HssChannelized operation */
++#define CHAN_FLOW_ENABLE 0x43
++#define CHAN_FLOW_DISABLE 0x44
++#define CHAN_IDLE_PATTERN_WRITE 0x45
++#define CHAN_NUM_CHANS_WRITE 0x46
++#define CHAN_RX_BUF_ADDR_WRITE 0x47
++#define CHAN_RX_BUF_CFG_WRITE 0x48
++#define CHAN_TX_BLK_CFG_WRITE 0x49
++#define CHAN_TX_BUF_ADDR_WRITE 0x4A
++#define CHAN_TX_BUF_SIZE_WRITE 0x4B
++#define CHAN_TSLOTSWITCH_ENABLE 0x4C
++#define CHAN_TSLOTSWITCH_DISABLE 0x4D
++
++/* downloads the gainWord value for a timeslot switching channel associated
++ with bypassNum */
++#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
++
++/* triggers the NPE to reset internal status and enable the HssPacketized
++ operation for the flow specified by pPipe */
++#define PKT_PIPE_FLOW_ENABLE 0x50
++#define PKT_PIPE_FLOW_DISABLE 0x51
++#define PKT_NUM_PIPES_WRITE 0x52
++#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
++#define PKT_PIPE_HDLC_CFG_WRITE 0x54
++#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
++#define PKT_PIPE_RX_SIZE_WRITE 0x56
++#define PKT_PIPE_MODE_WRITE 0x57
++
++/* HDLC packet status values - desc->status */
++#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
++#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
++#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
++#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
++ this packet (if buf_len < pkt_len) */
++#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
++#define ERR_HDLC_ABORT 6 /* abort sequence received */
++#define ERR_DISCONNECTING 7 /* disconnect is in progress */
++
++
++enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
++enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
++enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
++
++#ifdef __ARMEB__
++typedef struct sk_buff buffer_t;
++#define free_buffer dev_kfree_skb
++#define free_buffer_irq dev_kfree_skb_irq
++#else
++typedef void buffer_t;
++#define free_buffer kfree
++#define free_buffer_irq kfree
++#endif
++
++struct chan_device {
++ struct cdev cdev;
++ struct device *dev;
++ struct port *port;
++ unsigned int open_count, excl_open;
++ unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
++ unsigned long errors_bitmap;
++ u8 id, chan_count;
++ u8 log_channels[MAX_CHANNELS];
++};
++
++struct port {
++ struct device *dev;
++ struct npe *npe;
++ struct net_device *netdev;
++ struct napi_struct napi;
++ struct hss_plat_info *plat;
++ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
++ struct desc *desc_tab; /* coherent */
++ u32 desc_tab_phys;
++ unsigned int id;
++ atomic_t chan_tx_irq_number, chan_rx_irq_number;
++ wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
++ u8 hdlc_cfg;
++
++ /* the following fields must be protected by npe_lock */
++ enum mode mode;
++ unsigned int clock_type, clock_rate, loopback;
++ unsigned int frame_size, frame_sync_offset;
++
++ struct chan_device *chan_devices[MAX_CHAN_DEVICES];
++ u8 *chan_buf;
++ u32 chan_tx_buf_phys, chan_rx_buf_phys;
++ unsigned int chan_open_count, hdlc_open;
++ unsigned int chan_started, initialized, just_set_offset;
++ enum alignment aligned, carrier;
++ unsigned int chan_last_rx, chan_last_tx;
++ /* assigned channels, may be invalid with given frame length or mode */
++ u8 channels[MAX_CHANNELS];
++ int msg_count;
++};
++
++/* NPE message structure */
++struct msg {
++#ifdef __ARMEB__
++ u8 cmd, unused, hss_port, index;
++ union {
++ struct { u8 data8a, data8b, data8c, data8d; };
++ struct { u16 data16a, data16b; };
++ struct { u32 data32; };
++ };
++#else
++ u8 index, hss_port, unused, cmd;
++ union {
++ struct { u8 data8d, data8c, data8b, data8a; };
++ struct { u16 data16b, data16a; };
++ struct { u32 data32; };
++ };
++#endif
++};
++
++/* HDLC packet descriptor */
++struct desc {
++ u32 next; /* pointer to next buffer, unused */
++
++#ifdef __ARMEB__
++ u16 buf_len; /* buffer length */
++ u16 pkt_len; /* packet length */
++ u32 data; /* pointer to data buffer in RAM */
++ u8 status;
++ u8 error_count;
++ u16 __reserved;
++#else
++ u16 pkt_len; /* packet length */
++ u16 buf_len; /* buffer length */
++ u32 data; /* pointer to data buffer in RAM */
++ u16 __reserved;
++ u8 error_count;
++ u8 status;
++#endif
++ u32 __reserved1[4];
++};
++
++
++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ (n) * sizeof(struct desc))
++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
++
++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ ((n) + RX_DESCS) * sizeof(struct desc))
++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
++
++#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES)
++#define chan_tx_lists_len(port) (port->frame_size / 8 * CHAN_TX_LISTS * \
++ sizeof(u32))
++#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES)
++
++#define chan_tx_buf(port) ((port)->chan_buf)
++#define chan_tx_lists(port) (chan_tx_buf(port) + chan_tx_buf_len(port))
++#define chan_rx_buf(port) (chan_tx_lists(port) + chan_tx_lists_len(port))
++
++#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys + \
++ chan_tx_buf_len(port))
++
++static int hss_prepare_chan(struct port *port);
++void hss_chan_stop(struct port *port);
++
++/*****************************************************************************
++ * global variables
++ ****************************************************************************/
++
++static struct class *hss_class;
++static int chan_major;
++static int ports_open;
++static struct dma_pool *dma_pool;
++static spinlock_t npe_lock;
++
++static const struct {
++ int tx, txdone, rx, rxfree, chan;
++}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
++ HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
++ {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
++ HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
++};
++
++/*****************************************************************************
++ * utility functions
++ ****************************************************************************/
++
++static inline struct port* dev_to_port(struct net_device *dev)
++{
++ return dev_to_hdlc(dev)->priv;
++}
++
++static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
++{
++ return container_of(inode->i_cdev, struct chan_device, cdev);
++}
++
++#ifndef __ARMEB__
++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
++{
++ int i;
++ for (i = 0; i < cnt; i++)
++ dest[i] = swab32(src[i]);
++}
++#endif
++
++static int get_number(const char **buf, size_t *len, unsigned int *ptr,
++ unsigned int min, unsigned int max)
++{
++ char *endp;
++ unsigned long val = simple_strtoul(*buf, &endp, 10);
++
++ if (endp == *buf || endp - *buf > *len || val < min || val > max)
++ return -EINVAL;
++ *len -= endp - *buf;
++ *buf = endp;
++ *ptr = val;
++ return 0;
++}
++
++static int parse_channels(const char **buf, size_t *len, u8 *channels)
++{
++ unsigned int ch, next = 0;
++
++ if (*len && (*buf)[*len - 1] == '\n')
++ (*len)--;
++
++ memset(channels, 0, MAX_CHANNELS);
++
++ if (!*len)
++ return 0;
++
++ /* Format: "A,B-C,...", A > B > C */
++ while (1) {
++ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
++ return -EINVAL;
++ channels[ch] = 1;
++ next = ch + 1;
++ if (!*len)
++ break;
++ if (**buf == ',') {
++ (*buf)++;
++ (*len)--;
++ continue;
++ }
++ if (**buf != '-')
++ return -EINVAL;
++ (*buf)++;
++ (*len)--;
++ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
++ return -EINVAL;
++ while (next <= ch)
++ channels[next++] = 1;
++ if (!*len)
++ break;
++ if (**buf != ',')
++ return -EINVAL;
++ (*buf)++;
++ (*len)--;
++ }
++ return 1;
++}
++
++static size_t print_channels(struct port *port, char *buf, u8 id)
++{
++ unsigned int ch, cnt = 0;
++ size_t len = 0;
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (port->channels[ch] == id) {
++ if (cnt == 0) {
++ sprintf(buf + len, "%s%u", len ? "," : "", ch);
++ len += strlen(buf + len);
++ }
++ cnt++;
++ } else {
++ if (cnt > 1) {
++ sprintf(buf + len, "-%u", ch - 1);
++ len += strlen(buf + len);
++ }
++ cnt = 0;
++ }
++ if (cnt > 1) {
++ sprintf(buf + len, "-%u", ch - 1);
++ len += strlen(buf + len);
++ }
++
++ buf[len++] = '\n';
++ return len;
++}
++
++static inline unsigned int sub_offset(unsigned int a, unsigned int b,
++ unsigned int modulo)
++{
++ return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
++}
++
++/*****************************************************************************
++ * HSS access
++ ****************************************************************************/
++
++static void hss_config_load(struct port *port)
++{
++ struct msg msg;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_LOAD;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
++ break;
++ if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
++ break;
++
++ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
++ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
++ break;
++
++ /* HDLC may stop working without this */
++ npe_recv_message(port->npe, &msg, "FLUSH_IT");
++ return;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
++ port->id);
++ BUG();
++}
++
++static void hss_config_set_pcr(struct port *port)
++{
++ struct msg msg;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_TX_PCR;
++ msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
++ PCR_TX_DATA_ENABLE;
++ if (port->frame_size % 8 == 0)
++ msg.data32 |= PCR_SOF_NO_FBIT;
++ if (port->clock_type == CLOCK_INT)
++ msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
++ break;
++
++ msg.index = HSS_CONFIG_RX_PCR;
++ msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
++ break;
++ return;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
++ BUG();
++}
++
++static void hss_config_set_hdlc_cfg(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = port->hdlc_cfg; /* rx_cfg */
++ msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
++ " configuration\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_core(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_CORE_CR;
++ msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
++ (port->id ? CCR_SECOND_HSS : 0);
++ if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
++ " register\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_line(struct port *port)
++{
++ struct msg msg;
++
++ hss_config_set_pcr(port);
++ hss_config_set_core(port);
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_CLOCK_CR;
++ msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
++ " register\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_rx_frame(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_RX_FCR;
++ msg.data16a = port->frame_sync_offset;
++ msg.data16b = port->frame_size - 1;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
++ " and offset\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_frame(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_TX_FCR;
++ msg.data16a = TX_FRAME_SYNC_OFFSET;
++ msg.data16b = port->frame_size - 1;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
++ " and offset\n", port->id);
++ BUG();
++ }
++ hss_config_set_rx_frame(port);
++}
++
++static void hss_config_set_lut(struct port *port)
++{
++ struct msg msg;
++ int chan_count = 0, log_chan = 0, i, ch;
++ u32 lut[MAX_CHANNELS / 4];
++
++ memset(lut, 0, sizeof(lut));
++ for (i = 0; i < MAX_CHAN_DEVICES; i++)
++ if (port->chan_devices[i])
++ port->chan_devices[i]->chan_count = 0;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++) {
++ struct chan_device *chdev = NULL;
++ unsigned int entry;
++
++ if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
++ chdev = port->chan_devices[port->channels[ch]];
++
++ if (port->mode == MODE_G704 && ch == 0)
++ entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
++ else if (port->mode == MODE_HDLC ||
++ port->channels[ch] == CHANNEL_HDLC)
++ entry = TDMMAP_HDLC;
++ else if (chdev && chdev->open_count) {
++ entry = TDMMAP_VOICE64K;
++ chdev->log_channels[chdev->chan_count++] = log_chan;
++ } else
++ entry = TDMMAP_UNASSIGNED;
++ if (entry == TDMMAP_VOICE64K) {
++ chan_count++;
++ log_chan++;
++ }
++
++ msg.data32 >>= 2;
++ msg.data32 |= entry << 30;
++
++ if (ch % 16 == 15) {
++ msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
++ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
++ break;
++
++ msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
++ break;
++ }
++ }
++ if (ch != MAX_CHANNELS) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
++ " table\n", port->id);
++ BUG();
++ }
++
++ hss_config_set_frame(port);
++
++ if (!chan_count)
++ return;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_NUM_CHANS_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = chan_count;
++ if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
++ port->id);
++ BUG();
++ }
++
++ /* don't leak data */
++ // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
++ if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
++ for (i = 0; i < CHAN_TX_FRAMES; i += 4)
++ *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
++
++ for (i = 0; i < CHAN_TX_LISTS; i++) {
++ u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
++ u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
++ for (ch = 0; ch < chan_count; ch++)
++ list[ch] = phys + ch * CHAN_TX_FRAMES;
++ }
++ dma_sync_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port) + chan_tx_lists_len(port),
++ DMA_TO_DEVICE);
++}
++
++static u32 hss_config_get_status(struct port *port)
++{
++ struct msg msg;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_ERROR_READ;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
++ break;
++ if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
++ break;
++
++ return msg.data32;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
++ BUG();
++}
++
++static void hss_config_start_chan(struct port *port)
++{
++ struct msg msg;
++
++ port->chan_last_tx = 0;
++ port->chan_last_rx = 0;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
++ msg.hss_port = port->id;
++ msg.data32 = port->chan_rx_buf_phys;
++ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
++ msg.hss_port = port->id;
++ msg.data32 = chan_tx_lists_phys(port);
++ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_FLOW_ENABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
++ break;
++ port->chan_started = 1;
++ return;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
++ port->id);
++ BUG();
++}
++
++static void hss_config_stop_chan(struct port *port)
++{
++ struct msg msg;
++
++ if (!port->chan_started)
++ return;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_FLOW_DISABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
++ port->id);
++ BUG();
++ }
++ hss_config_get_status(port); /* make sure it's halted */
++}
++
++static void hss_config_start_hdlc(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FLOW_ENABLE;
++ msg.hss_port = port->id;
++ msg.data32 = 0;
++ if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
++ port->id);
++ BUG();
++ }
++}
++
++static void hss_config_stop_hdlc(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FLOW_DISABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
++ port->id);
++ BUG();
++ }
++ hss_config_get_status(port); /* make sure it's halted */
++}
++
++static int hss_config_load_firmware(struct port *port)
++{
++ struct msg msg;
++
++ if (port->initialized)
++ return 0;
++
++ if (!npe_running(port->npe)) {
++ int err;
++ if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
++ port->dev)))
++ return err;
++ }
++
++ do {
++ /* HSS main configuration */
++ hss_config_set_line(port);
++
++ hss_config_set_frame(port);
++
++ /* HDLC mode configuration */
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_NUM_PIPES_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = PKT_NUM_PIPES;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
++ break;
++
++ msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
++ msg.data8a = PKT_PIPE_FIFO_SIZEW;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
++ break;
++
++ msg.cmd = PKT_PIPE_MODE_WRITE;
++ msg.data8a = NPE_PKT_MODE_HDLC;
++ /* msg.data8b = inv_mask */
++ /* msg.data8c = or_mask */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
++ break;
++
++ msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
++ msg.data16a = HDLC_MAX_MRU; /* including CRC */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
++ break;
++
++ msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
++ msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
++ break;
++
++ /* Channelized operation settings */
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_TX_BLK_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
++ msg.data8a = msg.data8b / 4;
++ msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
++ msg.data8c = msg.data8d / 4;
++ if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_RX_BUF_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = CHAN_RX_TRIGGER / 8;
++ msg.data8b = CHAN_RX_FRAMES;
++ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = CHAN_TX_LISTS;
++ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
++ break;
++
++ port->initialized = 1;
++ return 0;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
++ BUG();
++}
++
++/*****************************************************************************
++ * packetized (HDLC) operation
++ ****************************************************************************/
++
++static inline void debug_pkt(struct net_device *dev, const char *func,
++ u8 *data, int len)
++{
++#if DEBUG_PKT_BYTES
++ int i;
++
++ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
++ for (i = 0; i < len; i++) {
++ if (i >= DEBUG_PKT_BYTES)
++ break;
++ printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
++ }
++ printk(KERN_DEBUG "\n");
++#endif
++}
++
++
++static inline void debug_desc(u32 phys, struct desc *desc)
++{
++#if DEBUG_DESC
++ printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
++ phys, desc->next, desc->buf_len, desc->pkt_len,
++ desc->data, desc->status, desc->error_count);
++#endif
++}
++
++static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
++{
++#if DEBUG_QUEUES
++ static struct {
++ int queue;
++ char *name;
++ } names[] = {
++ { HSS0_PKT_TX0_QUEUE, "TX#0 " },
++ { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
++ { HSS0_PKT_RX_QUEUE, "RX#0 " },
++ { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
++ { HSS1_PKT_TX0_QUEUE, "TX#1 " },
++ { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
++ { HSS1_PKT_RX_QUEUE, "RX#1 " },
++ { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
++ };
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(names); i++)
++ if (names[i].queue == queue)
++ break;
++
++ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
++ i < ARRAY_SIZE(names) ? names[i].name : "",
++ is_get ? "->" : "<-", phys);
++#endif
++}
++
++static inline u32 queue_get_entry(unsigned int queue)
++{
++ u32 phys = qmgr_get_entry(queue);
++ debug_queue(queue, 1, phys);
++ return phys;
++}
++
++static inline int queue_get_desc(unsigned int queue, struct port *port,
++ int is_tx)
++{
++ u32 phys, tab_phys, n_desc;
++ struct desc *tab;
++
++ if (!(phys = queue_get_entry(queue)))
++ return -1;
++
++ BUG_ON(phys & 0x1F);
++ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
++ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
++ n_desc = (phys - tab_phys) / sizeof(struct desc);
++ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
++ debug_desc(phys, &tab[n_desc]);
++ BUG_ON(tab[n_desc].next);
++ return n_desc;
++}
++
++static inline void queue_put_desc(unsigned int queue, u32 phys,
++ struct desc *desc)
++{
++ debug_queue(queue, 0, phys);
++ debug_desc(phys, desc);
++ BUG_ON(phys & 0x1F);
++ qmgr_put_entry(queue, phys);
++ BUG_ON(qmgr_stat_overflow(queue));
++}
++
++
++static inline void dma_unmap_tx(struct port *port, struct desc *desc)
++{
++#ifdef __ARMEB__
++ dma_unmap_single(&port->netdev->dev, desc->data,
++ desc->buf_len, DMA_TO_DEVICE);
++#else
++ dma_unmap_single(&port->netdev->dev, desc->data & ~3,
++ ALIGN((desc->data & 3) + desc->buf_len, 4),
++ DMA_TO_DEVICE);
++#endif
++}
++
++
++static void hss_hdlc_set_carrier(void *pdev, int carrier)
++{
++ struct net_device *netdev = pdev;
++ struct port *port = dev_to_port(netdev);
++ unsigned long flags;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ port->carrier = carrier;
++ if (!port->loopback) {
++ if (carrier)
++ netif_carrier_on(netdev);
++ else
++ netif_carrier_off(netdev);
++ }
++ spin_unlock_irqrestore(&npe_lock, flags);
++}
++
++static void hss_hdlc_rx_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = dev_to_port(dev);
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
++#endif
++ qmgr_disable_irq(queue_ids[port->id].rx);
++ netif_rx_schedule(dev, &port->napi);
++}
++
++static int hss_hdlc_poll(struct napi_struct *napi, int budget)
++{
++ struct port *port = container_of(napi, struct port, napi);
++ struct net_device *dev = port->netdev;
++ unsigned int rxq = queue_ids[port->id].rx;
++ unsigned int rxfreeq = queue_ids[port->id].rxfree;
++ struct net_device_stats *stats = hdlc_stats(dev);
++ int received = 0;
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
++#endif
++
++ while (received < budget) {
++ struct sk_buff *skb;
++ struct desc *desc;
++ int n;
++#ifdef __ARMEB__
++ struct sk_buff *temp;
++ u32 phys;
++#endif
++
++ if ((n = queue_get_desc(rxq, port, 0)) < 0) {
++ received = 0; /* No packet received */
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll"
++ " netif_rx_complete\n", dev->name);
++#endif
++ netif_rx_complete(dev, napi);
++ qmgr_enable_irq(rxq);
++ if (!qmgr_stat_empty(rxq) &&
++ netif_rx_reschedule(dev, napi)) {
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll"
++ " netif_rx_reschedule succeeded\n",
++ dev->name);
++#endif
++ qmgr_disable_irq(rxq);
++ continue;
++ }
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
++ dev->name);
++#endif
++ return 0; /* all work done */
++ }
++
++ desc = rx_desc_ptr(port, n);
++#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
++ if (desc->error_count)
++ printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
++ " errors %u\n", dev->name, desc->status,
++ desc->error_count);
++#endif
++ skb = NULL;
++ switch (desc->status) {
++ case 0:
++#ifdef __ARMEB__
++ if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
++ phys = dma_map_single(&dev->dev, skb->data,
++ RX_SIZE,
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(phys)) {
++ dev_kfree_skb(skb);
++ skb = NULL;
++ }
++ }
++#else
++ skb = netdev_alloc_skb(dev, desc->pkt_len);
++#endif
++ if (!skb)
++ stats->rx_dropped++;
++ break;
++ case ERR_HDLC_ALIGN:
++ case ERR_HDLC_ABORT:
++ stats->rx_frame_errors++;
++ stats->rx_errors++;
++ break;
++ case ERR_HDLC_FCS:
++ stats->rx_crc_errors++;
++ stats->rx_errors++;
++ break;
++ case ERR_HDLC_TOO_LONG:
++ stats->rx_length_errors++;
++ stats->rx_errors++;
++ break;
++ default: /* FIXME - remove printk */
++ printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
++ " errors %u\n", dev->name, desc->status,
++ desc->error_count);
++ stats->rx_errors++;
++ }
++
++ if (!skb) {
++ /* put the desc back on RX-ready queue */
++ desc->buf_len = RX_SIZE;
++ desc->pkt_len = desc->status = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ continue;
++ }
++
++ /* process received frame */
++#ifdef __ARMEB__
++ temp = skb;
++ skb = port->rx_buff_tab[n];
++ dma_unmap_single(&dev->dev, desc->data,
++ RX_SIZE, DMA_FROM_DEVICE);
++#else
++ dma_sync_single(&dev->dev, desc->data,
++ RX_SIZE, DMA_FROM_DEVICE);
++ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
++ ALIGN(desc->pkt_len, 4) / 4);
++#endif
++ skb_put(skb, desc->pkt_len);
++
++ debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
++
++ skb->protocol = hdlc_type_trans(skb, dev);
++ dev->last_rx = jiffies;
++ stats->rx_packets++;
++ stats->rx_bytes += skb->len;
++ netif_receive_skb(skb);
++
++ /* put the new buffer on RX-free queue */
++#ifdef __ARMEB__
++ port->rx_buff_tab[n] = temp;
++ desc->data = phys;
++#endif
++ desc->buf_len = RX_SIZE;
++ desc->pkt_len = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ received++;
++ }
++#if DEBUG_RX
++ printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
++#endif
++ return received; /* not all work done */
++}
++
++
++static void hss_hdlc_txdone_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = dev_to_port(dev);
++ struct net_device_stats *stats = hdlc_stats(dev);
++ int n_desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
++#endif
++ while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
++ port, 1)) >= 0) {
++ struct desc *desc;
++ int start;
++
++ desc = tx_desc_ptr(port, n_desc);
++
++ stats->tx_packets++;
++ stats->tx_bytes += desc->pkt_len;
++
++ dma_unmap_tx(port, desc);
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
++ dev->name, port->tx_buff_tab[n_desc]);
++#endif
++ free_buffer_irq(port->tx_buff_tab[n_desc]);
++ port->tx_buff_tab[n_desc] = NULL;
++
++ start = qmgr_stat_empty(port->plat->txreadyq);
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, n_desc), desc);
++ if (start) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
++ " ready\n", dev->name);
++#endif
++ netif_wake_queue(dev);
++ }
++ }
++}
++
++static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ struct net_device_stats *stats = hdlc_stats(dev);
++ unsigned int txreadyq = port->plat->txreadyq;
++ int len, offset, bytes, n;
++ void *mem;
++ u32 phys;
++ struct desc *desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
++#endif
++
++ if (unlikely(skb->len > HDLC_MAX_MRU)) {
++ dev_kfree_skb(skb);
++ stats->tx_errors++;
++ return NETDEV_TX_OK;
++ }
++
++ debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
++
++ len = skb->len;
++#ifdef __ARMEB__
++ offset = 0; /* no need to keep alignment */
++ bytes = len;
++ mem = skb->data;
++#else
++ offset = (int)skb->data & 3; /* keep 32-bit alignment */
++ bytes = ALIGN(offset + len, 4);
++ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
++ dev_kfree_skb(skb);
++ stats->tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
++ dev_kfree_skb(skb);
++#endif
++
++ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
++ if (dma_mapping_error(phys)) {
++#ifdef __ARMEB__
++ dev_kfree_skb(skb);
++#else
++ kfree(mem);
++#endif
++ stats->tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++
++ n = queue_get_desc(txreadyq, port, 1);
++ BUG_ON(n < 0);
++ desc = tx_desc_ptr(port, n);
++
++#ifdef __ARMEB__
++ port->tx_buff_tab[n] = skb;
++#else
++ port->tx_buff_tab[n] = mem;
++#endif
++ desc->data = phys + offset;
++ desc->buf_len = desc->pkt_len = len;
++
++ wmb();
++ queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
++ dev->trans_start = jiffies;
++
++ if (qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
++#endif
++ netif_stop_queue(dev);
++ /* we could miss TX ready interrupt */
++ if (!qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
++ dev->name);
++#endif
++ netif_wake_queue(dev);
++ }
++ }
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
++#endif
++ return NETDEV_TX_OK;
++}
++
++
++static int request_hdlc_queues(struct port *port)
++{
++ int err;
++
++ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
++ if (err)
++ return err;
++
++ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
++ if (err)
++ goto rel_rxfree;
++
++ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_rx;
++
++ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_tx;
++
++ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_txready;
++ return 0;
++
++rel_txready:
++ qmgr_release_queue(port->plat->txreadyq);
++rel_tx:
++ qmgr_release_queue(queue_ids[port->id].tx);
++rel_rx:
++ qmgr_release_queue(queue_ids[port->id].rx);
++rel_rxfree:
++ qmgr_release_queue(queue_ids[port->id].rxfree);
++ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
++ port->netdev->name);
++ return err;
++}
++
++static void release_hdlc_queues(struct port *port)
++{
++ qmgr_release_queue(queue_ids[port->id].rxfree);
++ qmgr_release_queue(queue_ids[port->id].rx);
++ qmgr_release_queue(queue_ids[port->id].txdone);
++ qmgr_release_queue(queue_ids[port->id].tx);
++ qmgr_release_queue(port->plat->txreadyq);
++}
++
++static int init_hdlc_queues(struct port *port)
++{
++ int i;
++
++ if (!ports_open)
++ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
++ POOL_ALLOC_SIZE, 32, 0)))
++ return -ENOMEM;
++
++ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
++ &port->desc_tab_phys)))
++ return -ENOMEM;
++ memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
++ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
++ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
++
++ /* Setup RX buffers */
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff;
++ void *data;
++#ifdef __ARMEB__
++ if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
++ return -ENOMEM;
++ data = buff->data;
++#else
++ if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
++ return -ENOMEM;
++ data = buff;
++#endif
++ desc->buf_len = RX_SIZE;
++ desc->data = dma_map_single(&port->netdev->dev, data,
++ RX_SIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(desc->data)) {
++ free_buffer(buff);
++ return -EIO;
++ }
++ port->rx_buff_tab[i] = buff;
++ }
++
++ return 0;
++}
++
++static void destroy_hdlc_queues(struct port *port)
++{
++ int i;
++
++ if (port->desc_tab) {
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff = port->rx_buff_tab[i];
++ if (buff) {
++ dma_unmap_single(&port->netdev->dev,
++ desc->data, RX_SIZE,
++ DMA_FROM_DEVICE);
++ free_buffer(buff);
++ }
++ }
++ for (i = 0; i < TX_DESCS; i++) {
++ struct desc *desc = tx_desc_ptr(port, i);
++ buffer_t *buff = port->tx_buff_tab[i];
++ if (buff) {
++ dma_unmap_tx(port, desc);
++ free_buffer(buff);
++ }
++ }
++ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
++ port->desc_tab = NULL;
++ }
++
++ if (!ports_open && dma_pool) {
++ dma_pool_destroy(dma_pool);
++ dma_pool = NULL;
++ }
++}
++
++static int hss_hdlc_open(struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ unsigned long flags;
++ int i, err = 0;
++
++ if ((err = hdlc_open(dev)))
++ return err;
++
++ if ((err = request_hdlc_queues(port)))
++ goto err_hdlc_close;
++
++ if ((err = init_hdlc_queues(port)))
++ goto err_destroy_queues;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
++ err = -EBUSY; /* channel #0 is used for G.704 framing */
++ goto err_unlock;
++ }
++ if (port->mode != MODE_HDLC)
++ for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
++ if (port->channels[i] == CHANNEL_HDLC) {
++ err = -ECHRNG; /* frame too short */
++ goto err_unlock;
++ }
++
++ if ((err = hss_config_load_firmware(port)))
++ goto err_unlock;
++
++ if (!port->chan_open_count && port->plat->open)
++ if ((err = port->plat->open(port->id, dev,
++ hss_hdlc_set_carrier)))
++ goto err_unlock;
++
++ if (port->mode == MODE_G704 && !port->chan_open_count)
++ if ((err = hss_prepare_chan(port)))
++ goto err_plat_close;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ /* Populate queues with buffers, no failure after this point */
++ for (i = 0; i < TX_DESCS; i++)
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, i), tx_desc_ptr(port, i));
++
++ for (i = 0; i < RX_DESCS; i++)
++ queue_put_desc(queue_ids[port->id].rxfree,
++ rx_desc_phys(port, i), rx_desc_ptr(port, i));
++
++ napi_enable(&port->napi);
++ netif_start_queue(dev);
++
++ qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_hdlc_rx_irq, dev);
++
++ qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_hdlc_txdone_irq, dev);
++ qmgr_enable_irq(queue_ids[port->id].txdone);
++
++ ports_open++;
++ port->hdlc_open = 1;
++
++ hss_config_set_hdlc_cfg(port);
++ hss_config_set_lut(port);
++ hss_config_load(port);
++
++ if (port->mode == MODE_G704 && !port->chan_open_count)
++ hss_config_start_chan(port);
++
++ hss_config_start_hdlc(port);
++
++ /* we may already have RX data, enables IRQ */
++ netif_rx_schedule(dev, &port->napi);
++ return 0;
++
++err_plat_close:
++ if (!port->chan_open_count && port->plat->close)
++ port->plat->close(port->id, dev);
++err_unlock:
++ spin_unlock_irqrestore(&npe_lock, flags);
++err_destroy_queues:
++ destroy_hdlc_queues(port);
++ release_hdlc_queues(port);
++err_hdlc_close:
++ hdlc_close(dev);
++ return err;
++}
++
++static int hss_hdlc_close(struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ unsigned long flags;
++ int i, buffs = RX_DESCS; /* allocated RX buffers */
++
++ spin_lock_irqsave(&npe_lock, flags);
++ ports_open--;
++ port->hdlc_open = 0;
++ qmgr_disable_irq(queue_ids[port->id].rx);
++ netif_stop_queue(dev);
++ napi_disable(&port->napi);
++
++ hss_config_stop_hdlc(port);
++
++ if (port->mode == MODE_G704 && !port->chan_open_count)
++ hss_chan_stop(port);
++
++ while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
++ buffs--;
++ while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
++ buffs--;
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
++ " left in NPE\n", dev->name, buffs);
++
++ buffs = TX_DESCS;
++ while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
++ buffs--; /* cancel TX */
++
++ i = 0;
++ do {
++ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
++ buffs--;
++ if (!buffs)
++ break;
++ } while (++i < MAX_CLOSE_WAIT);
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
++ "left in NPE\n", dev->name, buffs);
++#if DEBUG_CLOSE
++ if (!buffs)
++ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
++#endif
++ qmgr_disable_irq(queue_ids[port->id].txdone);
++
++ if (!port->chan_open_count && port->plat->close)
++ port->plat->close(port->id, dev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ destroy_hdlc_queues(port);
++ release_hdlc_queues(port);
++ hdlc_close(dev);
++ return 0;
++}
++
++
++static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
++ unsigned short parity)
++{
++ struct port *port = dev_to_port(dev);
++
++ if (encoding != ENCODING_NRZ)
++ return -EINVAL;
++
++ switch(parity) {
++ case PARITY_CRC16_PR1_CCITT:
++ port->hdlc_cfg = 0;
++ return 0;
++
++ case PARITY_CRC32_PR1_CCITT:
++ port->hdlc_cfg = PKT_HDLC_CRC_32;
++ return 0;
++
++ default:
++ return -EINVAL;
++ }
++}
++
++
++static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++ const size_t size = sizeof(sync_serial_settings);
++ sync_serial_settings new_line;
++ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
++ struct port *port = dev_to_port(dev);
++ unsigned long flags;
++ int i, clk;
++
++ if (cmd != SIOCWANDEV)
++ return hdlc_ioctl(dev, ifr, cmd);
++
++ switch(ifr->ifr_settings.type) {
++ case IF_GET_IFACE:
++ ifr->ifr_settings.type = IF_IFACE_V35;
++ if (ifr->ifr_settings.size < size) {
++ ifr->ifr_settings.size = size; /* data size wanted */
++ return -ENOBUFS;
++ }
++ memset(&new_line, 0, sizeof(new_line));
++ new_line.clock_type = port->clock_type;
++ new_line.clock_rate = port->clock_rate;
++ new_line.loopback = port->loopback;
++ if (copy_to_user(line, &new_line, size))
++ return -EFAULT;
++
++ if (!port->chan_buf)
++ return 0;
++
++ dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
++ chan_rx_buf_len(port), DMA_FROM_DEVICE);
++ printk(KERN_DEBUG "RX:\n");
++ for (i = 0; i < chan_rx_buf_len(port); i++) {
++ if (i % 32 == 0)
++ printk(KERN_DEBUG "%03X ", i);
++ printk("%02X%c", chan_rx_buf(port)[i],
++ (i + 1) % 32 ? ' ' : '\n');
++ }
++
++#if 0
++ printk(KERN_DEBUG "TX:\n");
++ for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
++ + chan_tx_lists_len(port); i++) {
++ if (i % 32 == 0)
++ printk(KERN_DEBUG "%03X ", i);
++ printk("%02X%c", chan_tx_buf(port)[i],
++ (i + 1) % 32 ? ' ' : '\n');
++ }
++#endif
++ port->msg_count = 10;
++ return 0;
++
++ case IF_IFACE_SYNC_SERIAL:
++ case IF_IFACE_V35:
++ if(!capable(CAP_NET_ADMIN))
++ return -EPERM;
++ if (copy_from_user(&new_line, line, size))
++ return -EFAULT;
++
++ clk = new_line.clock_type;
++ if (port->plat->set_clock)
++ clk = port->plat->set_clock(port->id, clk);
++
++ if (clk != CLOCK_EXT && clk != CLOCK_INT)
++ return -EINVAL; /* No such clock setting */
++
++ if (new_line.loopback != 0 && new_line.loopback != 1)
++ return -EINVAL;
++
++ port->clock_type = clk; /* Update settings */
++ /* FIXME port->clock_rate = new_line.clock_rate */;
++ port->loopback = new_line.loopback;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_line(port);
++ hss_config_load(port);
++ }
++ if (port->loopback || port->carrier)
++ netif_carrier_on(port->netdev);
++ else
++ netif_carrier_off(port->netdev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ return 0;
++
++ default:
++ return hdlc_ioctl(dev, ifr, cmd);
++ }
++}
++
++/*****************************************************************************
++ * channelized (G.704) operation
++ ****************************************************************************/
++
++static void g704_rx_framer(struct port *port, unsigned int offset)
++{
++ u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
++ CHAN_RX_FRAMES);
++ unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
++ unsigned int is_first = port->just_set_offset;
++ u8 zeros_even, zeros_odd, ones_even, ones_odd;
++ enum alignment aligned;
++
++ port->just_set_offset = 0;
++ dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
++ DMA_FROM_DEVICE);
++
++ /* check if aligned first */
++ for (frame = 0; frame < CHAN_RX_TRIGGER &&
++ (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
++ bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
++ u8 ve = data[frame];
++ u8 vo = data[frame + 1];
++
++ if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
++ bad_even++;
++
++ if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
++ bad_odd++;
++ }
++
++ if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
++ aligned = EVEN_FIRST;
++ else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
++ aligned = ODD_FIRST;
++ else
++ aligned = NOT_ALIGNED;
++
++ if (aligned != NOT_ALIGNED) {
++ if (aligned == port->aligned)
++ return; /* no change */
++ if (printk_ratelimit())
++ printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
++ " first)\n", port->id, port->frame_sync_offset,
++ aligned == EVEN_FIRST ? "even" : "odd");
++ port->aligned = aligned;
++
++ atomic_inc(&port->chan_tx_irq_number);
++ wake_up_interruptible(&port->chan_tx_waitq);
++ atomic_inc(&port->chan_rx_irq_number);
++ wake_up_interruptible(&port->chan_rx_waitq);
++ return;
++ }
++
++ /* not aligned */
++ if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
++ printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
++ port->aligned = NOT_ALIGNED;
++#if DEBUG_FRAMER
++ for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
++ printk("%c%02X%s", cnt == offset ? '>' : ' ',
++ chan_rx_buf(port)[cnt],
++ (cnt + 1) % 32 ? "" : "\n");
++#endif
++
++ for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
++ if (port->chan_devices[cnt]) {
++ set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
++ ->errors_bitmap);
++ set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
++ ->errors_bitmap);
++ }
++ atomic_inc(&port->chan_tx_irq_number);
++ wake_up_interruptible(&port->chan_tx_waitq);
++ atomic_inc(&port->chan_rx_irq_number);
++ wake_up_interruptible(&port->chan_rx_waitq);
++ }
++
++ if (is_first)
++ return;
++
++ zeros_even = zeros_odd = 0;
++ ones_even = ones_odd = 0xFF;
++ for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
++ zeros_even |= data[frame];
++ zeros_odd |= data[frame + 1];
++ ones_even &= data[frame];
++ ones_odd &= data[frame + 1];
++ }
++
++ for (bit = 0; bit < 7; bit++) {
++ if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
++ (ones_odd & 0x40) == 0x40) {
++ aligned = EVEN_FIRST; /* maybe */
++ break;
++ }
++ if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
++ (ones_even & 0x40) == 0x40) {
++ aligned = ODD_FIRST; /* maybe */
++ break;
++ }
++ zeros_even <<= 1;
++ ones_even = ones_even << 1 | 1;
++ zeros_odd <<= 1;
++ ones_odd = ones_odd << 1 | 1;
++ }
++
++ port->frame_sync_offset += port->frame_size - bit;
++ port->frame_sync_offset %= port->frame_size;
++ port->just_set_offset = 1;
++
++#if DEBUG_FRAMER
++ if (bit == 7)
++ printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
++ port->id, port->frame_sync_offset);
++ else
++ printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
++ " %u (%s frame first)\n", port->id,
++ port->frame_sync_offset,
++ aligned == EVEN_FIRST ? "even" : "odd");
++#endif
++
++ hss_config_set_rx_frame(port);
++ hss_config_load(port);
++}
++
++static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
++{
++ /* in bytes */
++ unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
++ unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
++ int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
++
++ offset *= list_len;
++ eaten = sub_offset(offset, last_offset, buff_len);
++
++ if (chan_dev->tx_count > eaten + 2 * list_len) {
++ /* two pages must be reserved for the transmitter */
++ chan_dev->tx_first += eaten;
++ chan_dev->tx_first %= buff_len;
++ chan_dev->tx_count -= eaten;
++ } else {
++ /* FIXME check
++ 0
++ 1 tx_first (may still be transmited)
++ 2 tx_offset (currently reported by the NPE)
++ 3 tx_first + 2 * list_len (free to write here)
++ 4
++ 5
++ */
++
++ /* printk(KERN_DEBUG "TX buffer underflow\n"); */
++ chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
++ chan_dev->tx_count = 2 * list_len; /* reserve */
++ set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
++ }
++}
++
++static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
++{
++ /* in bytes */
++ unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
++ unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
++ int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
++
++ offset *= chan_dev->chan_count;
++ chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
++ buff_len) + trig_len;
++ if (chan_dev->rx_count > buff_len - 2 * trig_len) {
++ /* two pages - offset[0] and offset[1] are lost - FIXME check */
++ /* printk(KERN_DEBUG "RX buffer overflow\n"); */
++ chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
++ chan_dev->rx_count = buff_len - 2 * trig_len;
++ set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
++ }
++}
++
++static void hss_chan_irq(void *pdev)
++{
++ struct port *port = pdev;
++ u32 v;
++
++#if DEBUG_RX
++ printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
++#endif
++ spin_lock(&npe_lock);
++ while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
++ unsigned int first, errors, tx_list, rx_frame;
++ int i, bad;
++
++ first = v >> 24;
++ errors = (v >> 16) & 0xFF;
++ tx_list = (v >> 8) & 0xFF;
++ rx_frame = v & 0xFF;
++
++ if (port->msg_count) {
++ printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
++ " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
++ " 0x%02X\n", port->id, jiffies, first, errors,
++ tx_list, rx_frame);
++ port->msg_count--;
++ }
++
++ BUG_ON(rx_frame % CHAN_RX_TRIGGER);
++ BUG_ON(rx_frame >= CHAN_RX_FRAMES);
++ BUG_ON(tx_list >= CHAN_TX_LISTS);
++
++ bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
++ if (!bad && tx_list != port->chan_last_tx) {
++ if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
++ printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
++ " current %i\n", port->chan_last_tx,
++ tx_list);
++ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
++ if (!port->chan_devices[i] ||
++ !port->chan_devices[i]->open_count)
++ continue;
++ chan_process_tx_irq(port->chan_devices[i],
++ tx_list);
++ }
++ atomic_inc(&port->chan_tx_irq_number);
++#if 0
++ printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
++ jiffies, errors);
++#endif
++ wake_up_interruptible(&port->chan_tx_waitq);
++ }
++
++ if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
++ CHAN_RX_FRAMES)
++ printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
++ " current %i\n", port->chan_last_rx, rx_frame);
++
++ if (port->mode == MODE_G704)
++ g704_rx_framer(port, rx_frame);
++
++ if (!bad &&
++ (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
++ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
++ if (!port->chan_devices[i] ||
++ !port->chan_devices[i]->open_count)
++ continue;
++ chan_process_rx_irq(port->chan_devices[i],
++ rx_frame);
++ }
++ atomic_inc(&port->chan_rx_irq_number);
++ wake_up_interruptible(&port->chan_rx_waitq);
++ }
++ port->chan_last_tx = tx_list;
++ port->chan_last_rx = rx_frame;
++ }
++ spin_unlock(&npe_lock);
++}
++
++
++static int hss_prepare_chan(struct port *port)
++{
++ int err;
++
++ if ((err = hss_config_load_firmware(port)))
++ return err;
++
++ if ((err = qmgr_request_queue(queue_ids[port->id].chan,
++ CHAN_QUEUE_LEN, 0, 0)))
++ return err;
++
++ if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
++ chan_tx_lists_len(port) +
++ chan_rx_buf_len(port), GFP_KERNEL))) {
++ goto release_queue;
++ err = -ENOBUFS;
++ }
++
++ port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
++ chan_tx_buf_len(port) +
++ chan_tx_lists_len(port),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(port->chan_tx_buf_phys)) {
++ err = -EIO;
++ goto free;
++ }
++
++ port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
++ chan_rx_buf_len(port),
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(port->chan_rx_buf_phys)) {
++ err = -EIO;
++ goto unmap_tx;
++ }
++
++ qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_chan_irq, port);
++ qmgr_enable_irq(queue_ids[port->id].chan);
++ hss_chan_irq(port);
++ return 0;
++
++unmap_tx:
++ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port) + chan_tx_lists_len(port),
++ DMA_TO_DEVICE);
++free:
++ kfree(port->chan_buf);
++ port->chan_buf = NULL;
++release_queue:
++ qmgr_release_queue(queue_ids[port->id].chan);
++ return err;
++}
++
++void hss_chan_stop(struct port *port)
++{
++ if (!port->chan_open_count && !port->hdlc_open)
++ qmgr_disable_irq(queue_ids[port->id].chan);
++
++ hss_config_stop_chan(port);
++ hss_config_set_lut(port);
++ hss_config_load(port);
++
++ if (!port->chan_open_count && !port->hdlc_open) {
++ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port) +
++ chan_tx_lists_len(port), DMA_TO_DEVICE);
++ dma_unmap_single(port->dev, port->chan_rx_buf_phys,
++ chan_rx_buf_len(port), DMA_FROM_DEVICE);
++ kfree(port->chan_buf);
++ port->chan_buf = NULL;
++ qmgr_release_queue(queue_ids[port->id].chan);
++ }
++}
++
++static int hss_chan_open(struct inode *inode, struct file *file)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev(inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ int i, err = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (chan_dev->open_count) {
++ if (chan_dev->excl_open || (file->f_flags & O_EXCL))
++ err = -EBUSY;
++ else
++ chan_dev->open_count++;
++ goto out;
++ }
++
++ if (port->mode == MODE_HDLC) {
++ err = -ENOSYS;
++ goto out;
++ }
++
++ if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
++ err = -EBUSY; /* channel #0 is used for G.704 signaling */
++ goto out;
++ }
++ for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
++ if (port->channels[i - 1] == chan_dev->id) {
++ err = -ECHRNG; /* frame too short */
++ goto out;
++ }
++
++ chan_dev->rx_first = chan_dev->tx_first = 0;
++ chan_dev->rx_count = chan_dev->tx_count = 0;
++ clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
++ clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
++
++ if (!port->chan_open_count && !port->hdlc_open) {
++ if (port->plat->open)
++ if ((err = port->plat->open(port->id, port->netdev,
++ hss_hdlc_set_carrier)))
++ goto out;
++ if ((err = hss_prepare_chan(port))) {
++ if (port->plat->close)
++ port->plat->close(port->id, port->netdev);
++ goto out;
++ }
++ }
++
++ hss_config_stop_chan(port);
++ chan_dev->open_count++;
++ port->chan_open_count++;
++ chan_dev->excl_open = !!file->f_flags & O_EXCL;
++
++ hss_config_set_lut(port);
++ hss_config_load(port);
++ hss_config_start_chan(port);
++out:
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static int hss_chan_release(struct inode *inode, struct file *file)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev(inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (!--chan_dev->open_count) {
++ if (!--port->chan_open_count && !port->hdlc_open) {
++ hss_chan_stop(port);
++ if (port->plat->close)
++ port->plat->close(port->id, port->netdev);
++ } else {
++ hss_config_stop_chan(port);
++ hss_config_set_lut(port);
++ hss_config_set_line(port); //
++ hss_config_start_chan(port);
++ }
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return 0;
++}
++
++static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
++ loff_t *f_pos)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev
++ (file->f_path.dentry->d_inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ u8 *rx_buf;
++ int res = 0, loops = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ while (1) {
++ int prev_irq = atomic_read(&port->chan_rx_irq_number);
++#if 0
++ if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
++ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
++ res = -EIO;
++ goto out;
++ }
++#endif
++ if (count == 0)
++ goto out; /* no need to wait */
++
++ if (chan_dev->rx_count)
++ break;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ loops++;
++ if ((res = wait_event_interruptible
++ (port->chan_rx_waitq,
++ atomic_read(&port->chan_rx_irq_number) != prev_irq)))
++ goto out;
++ spin_lock_irqsave(&npe_lock, flags);
++ continue;
++ }
++
++ dma_sync_single(port->dev, port->chan_rx_buf_phys,
++ chan_rx_buf_len(port), DMA_FROM_DEVICE);
++
++#if 0
++ if (loops > 1)
++ printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
++ " last_rx %u loops %i\n", chan_dev->rx_first,
++ chan_dev->rx_count, count, port->chan_last_rx, loops);
++#endif
++ rx_buf = chan_rx_buf(port);
++ while (chan_dev->rx_count > 0 && res < count) {
++ unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
++ unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
++
++ chan = chan_dev->log_channels[chan];
++ if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
++ res = -EFAULT;
++ goto out;
++ }
++ chan_dev->rx_first++;
++ chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
++ chan_dev->rx_count--;
++ res++;
++ }
++out:
++#if 0
++ printk(KERN_DEBUG "EXIT rx_first %u rx_count %u res %i\n",
++ chan_dev->rx_first, chan_dev->rx_count, res);
++#endif
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return res;
++}
++
++static ssize_t hss_chan_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev
++ (file->f_path.dentry->d_inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ u8 *tx_buf;
++ int res = 0, loops = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ while (1) {
++ int prev_irq = atomic_read(&port->chan_tx_irq_number);
++#if 0
++ if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
++ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
++ res = -EIO;
++ goto out;
++ }
++#endif
++ if (count == 0)
++ goto out; /* no need to wait */
++
++ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
++ break;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ loops++;
++ if ((res = wait_event_interruptible
++ (port->chan_tx_waitq,
++ atomic_read (&port->chan_tx_irq_number) != prev_irq)))
++ goto out;
++ spin_lock_irqsave(&npe_lock, flags);
++ continue;
++ }
++
++#if 0
++ if (loops > 1)
++ printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
++ " last_tx %u loops %i\n", chan_dev->tx_first,
++ chan_dev->tx_count, count, port->chan_last_tx, loops);
++#endif
++ tx_buf = chan_tx_buf(port);
++ while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
++ res < count) {
++ unsigned int tail, chan, frame;
++
++ tail = (chan_dev->tx_first + chan_dev->tx_count) %
++ (CHAN_TX_FRAMES * chan_dev->chan_count);
++ chan = tail % chan_dev->chan_count;
++ frame = tail / chan_dev->chan_count;
++ chan = chan_dev->log_channels[chan];
++
++ if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
++ printk(KERN_DEBUG "BUG? TX %u %u %u\n",
++ tail, chan, frame);
++ res = -EFAULT;
++ goto out_sync;
++ }
++ chan_dev->tx_count++;
++ res++;
++ }
++out_sync:
++ dma_sync_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port), DMA_TO_DEVICE);
++out:
++#if 0
++ printk(KERN_DEBUG "EXIT TX_first %u tx_count %u res %i\n",
++ chan_dev->tx_first, chan_dev->tx_count, res);
++#endif
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return res;
++}
++
++
++static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev
++ (file->f_path.dentry->d_inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ unsigned int mask = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ poll_wait(file, &port->chan_tx_waitq, wait);
++ poll_wait(file, &port->chan_rx_waitq, wait);
++
++ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
++ mask |= POLLOUT | POLLWRNORM;
++ if (chan_dev->rx_count)
++ mask |= POLLIN | POLLRDNORM;
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return mask;
++}
++
++/*****************************************************************************
++ * channelized device sysfs attributes
++ ****************************************************************************/
++
++static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ struct chan_device *chan_dev = dev_get_drvdata(dev);
++
++ return print_channels(chan_dev->port, buf, chan_dev->id);
++}
++
++static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct chan_device *chan_dev = dev_get_drvdata(dev);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ unsigned int ch;
++ size_t orig_len = len;
++ int err;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (len != 7 || memcmp(buf, "destroy", 7))
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ cdev_del(&chan_dev->cdev);
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (port->channels[ch] == chan_dev->id)
++ port->channels[ch] = CHANNEL_UNUSED;
++ port->chan_devices[chan_dev->id] = NULL;
++ kfree(chan_dev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ if ((err = device_schedule_callback(dev, device_unregister)))
++ return err;
++ return orig_len;
++}
++
++static struct device_attribute chan_attr =
++ __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
++
++/*****************************************************************************
++ * main sysfs attributes
++ ****************************************************************************/
++
++static const struct file_operations chan_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .read = hss_chan_read,
++ .write = hss_chan_write,
++ .poll = hss_chan_poll,
++ .open = hss_chan_open,
++ .release = hss_chan_release,
++};
++
++static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ struct chan_device *chan_dev;
++ u8 channels[MAX_CHANNELS];
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int ch, id;
++ int minor, err;
++
++ if ((err = parse_channels(&buf, &len, channels)) < 1)
++ return err;
++
++ if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
++ return -ENOBUFS;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
++ err = -EINVAL;
++ goto free;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
++ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
++ err = -EBUSY;
++ goto free;
++ }
++
++ for (id = 0; id < MAX_CHAN_DEVICES; id++)
++ if (port->chan_devices[id] == NULL)
++ break;
++
++ if (id == MAX_CHAN_DEVICES) {
++ err = -EBUSY;
++ goto free;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch])
++ break;
++
++ minor = port->id * MAX_CHAN_DEVICES + ch;
++ chan_dev->id = id;
++ chan_dev->port = port;
++ chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
++ "hss%uch%u", port->id, ch);
++ if (IS_ERR(chan_dev->dev)) {
++ err = PTR_ERR(chan_dev->dev);
++ goto free;
++ }
++
++ cdev_init(&chan_dev->cdev, &chan_fops);
++ chan_dev->cdev.owner = THIS_MODULE;
++ if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
++ goto destroy_device;
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch])
++ port->channels[ch] = id;
++ port->chan_devices[id] = chan_dev;
++ dev_set_drvdata(chan_dev->dev, chan_dev);
++ BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++
++destroy_device:
++ device_unregister(chan_dev->dev);
++free:
++ kfree(chan_dev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
++}
++
++static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ u8 channels[MAX_CHANNELS];
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int ch;
++ int err;
++
++ if ((err = parse_channels(&buf, &len, channels)) < 0)
++ return err;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
++ err = -EINVAL;
++ goto err;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch] &&
++ port->channels[ch] != CHANNEL_UNUSED &&
++ port->channels[ch] != CHANNEL_HDLC) {
++ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
++ err = -EBUSY;
++ goto err;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch])
++ port->channels[ch] = CHANNEL_HDLC;
++ else if (port->channels[ch] == CHANNEL_HDLC)
++ port->channels[ch] = CHANNEL_UNUSED;
++
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_lut(port);
++ hss_config_load(port);
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++
++err:
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static ssize_t show_clock_type(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
++ return 5;
++}
++
++static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int clk, err;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (len != 3)
++ return -EINVAL;
++ if (!memcmp(buf, "ext", 3))
++ clk = CLOCK_EXT;
++ else if (!memcmp(buf, "int", 3))
++ clk = CLOCK_INT;
++ else
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ if (port->plat->set_clock)
++ clk = port->plat->set_clock(port->id, clk);
++ if (clk != CLOCK_EXT && clk != CLOCK_INT) {
++ err = -EINVAL; /* plat->set_clock shouldn't change the state */
++ goto err;
++ }
++ port->clock_type = clk;
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_line(port);
++ hss_config_load(port);
++ }
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ return orig_len;
++err:
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static ssize_t show_clock_rate(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ sprintf(buf, "%u\n", port->clock_rate);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++#if 0
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int rate;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
++ return -EINVAL;
++ if (len)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ port->clock_rate = rate;
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++#endif
++ return -EINVAL; /* FIXME not yet supported */
++}
++
++static ssize_t show_frame_size(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ if (port->mode != MODE_RAW && port->mode != MODE_G704)
++ return -EINVAL;
++
++ sprintf(buf, "%u\n", port->frame_size);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t ret = len;
++ unsigned long flags;
++ unsigned int size;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
++ return -EINVAL;
++ if (len || size % 8 > 1)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ if (port->mode != MODE_RAW && port->mode != MODE_G704)
++ ret = -EINVAL;
++ else if (!port->chan_open_count && !port->hdlc_open)
++ ret = -EBUSY;
++ else {
++ port->frame_size = size;
++ port->frame_sync_offset = 0;
++ }
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return ret;
++}
++
++static ssize_t show_frame_offset(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ sprintf(buf, "%u\n", port->frame_sync_offset);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_frame_offset(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int offset;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
++ return -EINVAL;
++ if (len)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ port->frame_sync_offset = offset;
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_rx_frame(port);
++ hss_config_load(port);
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++}
++
++static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ sprintf(buf, "%u\n", port->loopback);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int lb;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &lb, 0, 1))
++ return -EINVAL;
++ if (len)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->loopback != lb) {
++ port->loopback = lb;
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_core(port);
++ hss_config_load(port);
++ }
++ if (port->loopback || port->carrier)
++ netif_carrier_on(port->netdev);
++ else
++ netif_carrier_off(port->netdev);
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++}
++
++static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ switch(port->mode) {
++ case MODE_RAW:
++ strcpy(buf, "raw\n");
++ break;
++ case MODE_G704:
++ strcpy(buf, "g704\n");
++ break;
++ default:
++ strcpy(buf, "hdlc\n");
++ break;
++ }
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t ret = len;
++ unsigned long flags;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->chan_open_count || port->hdlc_open) {
++ ret = -EBUSY;
++ } else if (len == 4 && !memcmp(buf, "hdlc", 4))
++ port->mode = MODE_HDLC;
++ else if (len == 3 && !memcmp(buf, "raw", 3))
++ port->mode = MODE_RAW;
++ else if (len == 4 && !memcmp(buf, "g704", 4))
++ port->mode = MODE_G704;
++ else
++ ret = -EINVAL;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return ret;
++}
++
++static struct device_attribute hss_attrs[] = {
++ __ATTR(create_chan, 0200, NULL, create_chan),
++ __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
++ __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
++ __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
++ __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
++ __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
++ __ATTR(loopback, 0644, show_loopback, set_loopback),
++ __ATTR(mode, 0644, show_mode, set_mode),
++};
++
++/*****************************************************************************
++ * initialization
++ ****************************************************************************/
++
++static int __devinit hss_init_one(struct platform_device *pdev)
++{
++ struct port *port;
++ struct net_device *dev;
++ hdlc_device *hdlc;
++ int i, err;
++
++ if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
++ return -ENOMEM;
++ platform_set_drvdata(pdev, port);
++ port->id = pdev->id;
++
++ if ((port->npe = npe_request(0)) == NULL) {
++ err = -ENOSYS;
++ goto err_free;
++ }
++
++ port->dev = &pdev->dev;
++ port->plat = pdev->dev.platform_data;
++ if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
++ err = -ENOMEM;
++ goto err_plat;
++ }
++
++ SET_NETDEV_DEV(dev, &pdev->dev);
++ hdlc = dev_to_hdlc(dev);
++ hdlc->attach = hss_hdlc_attach;
++ hdlc->xmit = hss_hdlc_xmit;
++ dev->open = hss_hdlc_open;
++ dev->stop = hss_hdlc_close;
++ dev->do_ioctl = hss_hdlc_ioctl;
++ dev->tx_queue_len = 100;
++ port->clock_type = CLOCK_EXT;
++ port->clock_rate = 2048000;
++ port->frame_size = 256; /* E1 */
++ memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
++ init_waitqueue_head(&port->chan_tx_waitq);
++ init_waitqueue_head(&port->chan_rx_waitq);
++ netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
++
++ if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
++ goto err_free_netdev;
++
++ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
++ BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
++
++ printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
++ return 0;
++
++err_free_netdev:
++ free_netdev(dev);
++err_plat:
++ npe_release(port->npe);
++ platform_set_drvdata(pdev, NULL);
++err_free:
++ kfree(port);
++ return err;
++}
++
++static int __devexit hss_remove_one(struct platform_device *pdev)
++{
++ struct port *port = platform_get_drvdata(pdev);
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
++ device_remove_file(port->dev, &hss_attrs[i]);
++
++ unregister_hdlc_device(port->netdev);
++ free_netdev(port->netdev);
++ npe_release(port->npe);
++ platform_set_drvdata(pdev, NULL);
++ kfree(port);
++ return 0;
++}
++
++static struct platform_driver drv = {
++ .driver.name = DRV_NAME,
++ .probe = hss_init_one,
++ .remove = hss_remove_one,
++};
++
++static int __init hss_init_module(void)
++{
++ int err;
++ dev_t rdev;
++
++ if ((ixp4xx_read_feature_bits() &
++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
++ return -ENOSYS;
++
++ if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
++ "hss")))
++ return err;
++
++ spin_lock_init(&npe_lock);
++
++ if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
++ printk(KERN_ERR "Can't register device class 'hss'\n");
++ err = PTR_ERR(hss_class);
++ goto free_chrdev;
++ }
++ if ((err = platform_driver_register(&drv)))
++ goto destroy_class;
++
++ chan_major = MAJOR(rdev);
++ return 0;
++
++destroy_class:
++ class_destroy(hss_class);
++free_chrdev:
++ unregister_chrdev_region(MKDEV(chan_major, 0),
++ HSS_COUNT * MAX_CHAN_DEVICES);
++ return err;
++}
++
++static void __exit hss_cleanup_module(void)
++{
++ platform_driver_unregister(&drv);
++ class_destroy(hss_class);
++ unregister_chrdev_region(MKDEV(chan_major, 0),
++ HSS_COUNT * MAX_CHAN_DEVICES);
++}
++
++MODULE_AUTHOR("Krzysztof Halasa");
++MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:ixp4xx_hss");
++module_init(hss_init_module);
++module_exit(hss_cleanup_module);
===================================================================
--- linux-2.6.24.2.orig/arch/arm/mach-ixp4xx/avila-setup.c
+++ linux-2.6.24.2/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -132,12 +132,42 @@ static struct platform_device avila_pata
+@@ -132,6 +132,31 @@ static struct platform_device avila_pata
.resource = avila_pata_resources,
};
+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info avila_plat_eth[] = {
-+ {
-+ .phy = 0,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 1,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
++static struct eth_plat_info avila_npeb_data = {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
+};
+
-+static struct platform_device avila_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = avila_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = avila_plat_eth + 1,
-+ }
++static struct eth_plat_info avila_npec_data = {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++};
++
++static struct platform_device avila_npeb_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = &avila_npeb_data,
++};
++
++static struct platform_device avila_npec_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = &avila_npec_data,
+};
+
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
- &avila_uart
- };
-
-+static struct platform_device *avila_eth_devices[] = {
-+ &avila_eth[0],
-+ &avila_eth[1]
-+};
-+
- static void __init avila_init(void)
- {
- ixp4xx_sys_init();
-@@ -159,6 +189,7 @@ static void __init avila_init(void)
+@@ -159,6 +184,8 @@ static void __init avila_init(void)
platform_device_register(&avila_pata);
-+ platform_add_devices(avila_eth_devices, ARRAY_SIZE(avila_eth_devices));
++ platform_device_register(avila_npeb_device);
++ platform_device_register(avila_npec_device);
}
MACHINE_START(AVILA, "Gateworks Avila Network Platform")
+++ /dev/null
-diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/avila-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/avila-setup.c
---- linux-2.6.23.orig/arch/arm/mach-ixp4xx/avila-setup.c 2007-10-09 15:31:38.000000000 -0500
-+++ linux-2.6.23/arch/arm/mach-ixp4xx/avila-setup.c 2007-10-11 01:08:21.000000000 -0500
-@@ -138,6 +138,35 @@ static struct platform_device *avila_dev
- &avila_uart
- };
-
-+static char avila_rtc_probe[] __initdata = "rtc-ds1672.probe=0,0x68 ";
-+
-+static void __init avila_fixup(struct machine_desc *desc,
-+ struct tag *tags, char **cmdline, struct meminfo *mi)
-+{
-+ struct tag *t = tags;
-+ char *p = *cmdline;
-+
-+ /* Find the end of the tags table, taking note of any cmdline tag. */
-+ for (; t->hdr.size; t = tag_next(t)) {
-+ if (t->hdr.tag == ATAG_CMDLINE) {
-+ p = t->u.cmdline.cmdline;
-+ }
-+ }
-+
-+ /* Overwrite the end of the table with a new cmdline tag. */
-+ t->hdr.tag = ATAG_CMDLINE;
-+ t->hdr.size = (sizeof (struct tag_header) +
-+ strlen(avila_rtc_probe) + strlen(p) + 1 + 4) >> 2;
-+ strlcpy(t->u.cmdline.cmdline, avila_rtc_probe, COMMAND_LINE_SIZE);
-+ strlcpy(t->u.cmdline.cmdline + strlen(avila_rtc_probe), p,
-+ COMMAND_LINE_SIZE - strlen(avila_rtc_probe));
-+
-+ /* Terminate the table. */
-+ t = tag_next(t);
-+ t->hdr.tag = ATAG_NONE;
-+ t->hdr.size = 0;
-+}
-+
- static void __init avila_init(void)
- {
- ixp4xx_sys_init();
-@@ -165,6 +194,7 @@ MACHINE_START(AVILA, "Gateworks Avila Ne
- /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .fixup = avila_fixup,
- .map_io = ixp4xx_map_io,
- .init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
-@@ -182,6 +212,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc
- /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .fixup = avila_fixup,
- .map_io = ixp4xx_map_io,
- .init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
#include <linux/i2c-gpio.h>
#include <asm/types.h>
-@@ -177,6 +185,118 @@ static struct platform_device *avila_eth
- &avila_eth[1]
- };
+@@ -29,6 +37,13 @@
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
-+#ifdef CONFIG_SENSORS_EEPROM
+struct avila_board_info {
-+ unsigned char *model;
-+ int npes_used;
-+ int npeb_phy;
-+ int npec_phy;
++ unsigned char *model;
++ void (* setup)(void);
+};
+
-+static struct avila_board_info avila_boards[] = {
++static struct avila_board_info *avila_info __initdata;
++
+ static struct flash_platform_data avila_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+@@ -192,10 +207,160 @@ static void __init avila_fixup(struct ma
+ t->hdr.size = 0;
+ }
+
++static void __init avila_gw23xx_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_npec_device);
++}
++
++#ifdef CONFIG_SENSORS_EEPROM
++static void __init avila_gw2342_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2345_setup(void)
++{
++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
++ platform_device_register(&avila_npeb_device);
++
++ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2347_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++}
++
++static void __init avila_gw2348_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2353_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++}
++
++static void __init avila_gw2355_setup(void)
++{
++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
++ platform_device_register(&avila_npeb_device);
++
++ avila_npec_data.phy = 16;
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2357_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++}
++
++static struct avila_board_info avila_boards[] __initdata = {
+ {
+ .model = "GW2342",
-+ .npes_used = 2,
-+ .npeb_phy = 0,
-+ .npec_phy = 1,
++ .setup = avila_gw2342_setup,
+ }, {
-+ .model = "GW2347",
-+ .npes_used = 1,
-+ .npeb_phy = 1,
++ .model = "GW2345",
++ .setup = avila_gw2345_setup,
+ }, {
-+ .model = "GW2348-2",
-+ .npes_used = 2,
-+ .npeb_phy = 0,
-+ .npec_phy = 1,
++ .model = "GW2347",
++ .setup = avila_gw2347_setup,
+ }, {
-+ .model = "GW2348-4",
-+ .npes_used = 2,
-+ .npeb_phy = 0,
-+ .npec_phy = 1,
++ .model = "GW2348",
++ .setup = avila_gw2348_setup,
+ }, {
+ .model = "GW2353",
-+ .npes_used = 1,
-+ .npeb_phy = 1,
++ .setup = avila_gw2353_setup,
+ }, {
+ .model = "GW2355",
-+ .npes_used = 2,
-+ .npeb_phy = -1,
-+ .npec_phy = 1,
++ .setup = avila_gw2355_setup,
+ }, {
+ .model = "GW2357",
-+ .npes_used = 1,
-+ .npeb_phy = 1,
++ .setup = avila_gw2357_setup,
+ }
+};
+
-+static struct avila_board_info *avila_find_board_info(char *model)
++static struct avila_board_info * __init avila_find_board_info(char *model)
+{
+ int i;
+
+ unsigned char model[16];
+};
+
-+static int avila_eeprom_notify(struct notifier_block *self,
++static int __init avila_eeprom_notify(struct notifier_block *self,
+ unsigned long event, void *t)
+{
+ struct eeprom_data *ee = t;
-+ struct avila_board_info *info = NULL;
+ struct avila_eeprom_header hdr;
+
++ if (avila_info)
++ return NOTIFY_DONE;
++
+ /* The eeprom is at address 0x51 */
+ if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
+ return NOTIFY_DONE;
+
+ ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
-+ 0, sizeof(hdr));
++ 0, sizeof(hdr));
+
+ if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
+ return NOTIFY_DONE;
+
-+ memcpy(&avila_plat_eth[0].hwaddr, hdr.mac0, ETH_ALEN);
-+ memcpy(&avila_plat_eth[1].hwaddr, hdr.mac1, ETH_ALEN);
-+
-+ info = avila_find_board_info(hdr.model);
-+
-+ if (info) {
-+ printk(KERN_DEBUG "Running on Gateworks Avila %s\n",
-+ info->model);
-+ avila_plat_eth[0].phy = info->npeb_phy;
-+ avila_plat_eth[1].phy = info->npec_phy;
-+ platform_add_devices(avila_eth_devices,
-+ info->npes_used);
-+ } else {
-+ printk(KERN_INFO "Unknown/missing Avila model number"
-+ " -- defaults will be used\n");
-+ platform_add_devices(avila_eth_devices,
-+ ARRAY_SIZE(avila_eth_devices));
-+ }
++ memcpy(&avila_npeb_data.hwaddr, hdr.mac0, ETH_ALEN);
++ memcpy(&avila_npec_data.hwaddr, hdr.mac1, ETH_ALEN);
+
-+ unregister_eeprom_notifier(self);
++ avila_info = avila_find_board_info(hdr.model);
+
+ return NOTIFY_OK;
+}
+
-+static struct notifier_block avila_eeprom_notifier = {
++static struct notifier_block avila_eeprom_notifier __initdata = {
+ .notifier_call = avila_eeprom_notify
+};
-+#endif
++
++static void __init avila_register_eeprom_notifier(void)
++{
++ register_eeprom_notifier(&avila_eeprom_notifier);
++}
++
++static void __init avila_unregister_eeprom_notifier(void)
++{
++ unregister_eeprom_notifier(&avila_eeprom_notifier);
++}
++#else /* CONFIG_SENSORS_EEPROM */
++static inline void avila_register_eeprom_notifier(void) {};
++static inline void avila_unregister_eeprom_notifier(void) {};
++#endif /* CONFIG_SENSORS_EEPROM */
+
static void __init avila_init(void)
{
ixp4xx_sys_init();
-@@ -201,7 +321,11 @@ static void __init avila_init(void)
+
++ /*
++ * These devices are present on all Avila models and don't need any
++ * model specific setup.
++ */
+ avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ avila_flash_resource.end =
+ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+@@ -213,9 +378,28 @@ static void __init avila_init(void)
platform_device_register(&avila_pata);
-+#ifdef CONFIG_SENSORS_EEPROM
-+ register_eeprom_notifier(&avila_eeprom_notifier);
-+#else
- platform_add_devices(avila_eth_devices, ARRAY_SIZE(avila_eth_devices));
-+#endif
+- platform_device_register(avila_npeb_device);
+- platform_device_register(avila_npec_device);
++ avila_register_eeprom_notifier();
++}
++
++static int __init avila_model_setup(void)
++{
++ if (!machine_is_avila())
++ return 0;
++
++ if (avila_info) {
++ printk(KERN_DEBUG "Running on Gateworks Avila %s\n",
++ avila_info->model);
++ avila_info->setup();
++ } else {
++ printk(KERN_INFO "Unknown/missing Avila model number"
++ " -- defaults will be used\n");
++ avila_gw23xx_setup();
++ }
++
++ avila_unregister_eeprom_notifier();
++ return 0;
}
++late_initcall(avila_model_setup);
MACHINE_START(AVILA, "Gateworks Avila Network Platform")
+ /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
===================================================================
--- linux-2.6.24.2.orig/include/asm-arm/arch-ixp4xx/avila.h
+++ linux-2.6.24.2/include/asm-arm/arch-ixp4xx/avila.h
-@@ -36,4 +36,5 @@
+@@ -36,4 +36,6 @@
#define AVILA_PCI_INTC_PIN 9
#define AVILA_PCI_INTD_PIN 8
-
-+/* User LED */
-+#define AVILA_LED_USER_GPIO 3
++/* User LEDs */
++#define AVILA_GW23XX_LED_USER_GPIO 3
++#define AVILA_GW23X7_LED_USER_GPIO 4
Index: linux-2.6.24.2/arch/arm/mach-ixp4xx/avila-setup.c
===================================================================
--- linux-2.6.24.2.orig/arch/arm/mach-ixp4xx/avila-setup.c
+++ linux-2.6.24.2/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -174,10 +174,31 @@ static struct platform_device avila_eth[
- }
+@@ -26,6 +26,7 @@
+ # include <linux/eeprom.h>
+ #endif
+
++#include <linux/leds.h>
+ #include <linux/i2c-gpio.h>
+
+ #include <asm/types.h>
+@@ -172,6 +173,25 @@ static struct platform_device avila_npec
+ .dev.platform_data = &avila_npec_data,
};
-+#ifdef CONFIG_LEDS_IXP4XX
-+static struct resource avila_led_resources[] = {
++static struct gpio_led avila_leds[] = {
+ {
-+ .name = "user",
-+ .start = AVILA_LED_USER_GPIO,
-+ .end = AVILA_LED_USER_GPIO,
-+ .flags = IXP4XX_GPIO_LOW,
-+ },
++ .name = "user", /* green led */
++ .gpio = AVILA_GW23XX_LED_USER_GPIO,
++ .active_low = 1,
++ }
++};
++
++static struct gpio_led_platform_data avila_leds_data = {
++ .num_leds = 1,
++ .leds = avila_leds,
+};
+
-+static struct platform_device avila_leds = {
-+ .name = "IXP4XX-GPIO-LED",
++static struct platform_device avila_leds_device = {
++ .name = "leds-gpio",
+ .id = -1,
-+ .num_resources = ARRAY_SIZE(avila_led_resources),
-+ .resource = avila_led_resources,
++ .dev.platform_data = &avila_leds_data,
+};
-+#endif
+
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
-- &avila_uart
-+ &avila_uart,
-+#ifdef CONFIG_LEDS_IXP4XX
-+ &avila_leds,
-+#endif
- };
+@@ -211,6 +231,8 @@ static void __init avila_gw23xx_setup(vo
+ {
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_leds_device);
+ }
+
+ #ifdef CONFIG_SENSORS_EEPROM
+@@ -218,6 +240,8 @@ static void __init avila_gw2342_setup(vo
+ {
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_leds_device);
+ }
+
+ static void __init avila_gw2345_setup(void)
+@@ -228,22 +252,30 @@ static void __init avila_gw2345_setup(vo
+
+ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_leds_device);
+ }
+
+ static void __init avila_gw2347_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
++
++ avila_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
++ platform_device_register(&avila_leds_device);
+ }
+
+ static void __init avila_gw2348_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_leds_device);
+ }
+
+ static void __init avila_gw2353_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_leds_device);
+ }
+
+ static void __init avila_gw2355_setup(void)
+@@ -254,11 +286,16 @@ static void __init avila_gw2355_setup(vo
+
+ avila_npec_data.phy = 5;
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_leds_device);
+ }
+
+ static void __init avila_gw2357_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
++
++ avila_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
++ platform_device_register(&avila_leds_device);
+ }
- static struct platform_device *avila_eth_devices[] = {
+ static struct avila_board_info avila_boards[] __initdata = {
===================================================================
--- linux-2.6.24.2.orig/arch/arm/mach-ixp4xx/avila-setup.c
+++ linux-2.6.24.2/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -192,6 +192,24 @@ static struct platform_device avila_leds
+@@ -192,10 +192,28 @@ static struct platform_device avila_leds
+ .dev.platform_data = &avila_leds_data,
};
- #endif
-+#ifdef CONFIG_GPIO_DEVICE
+static struct resource avila_gpio_resources[] = {
+ {
+ .name = "gpio",
++ /* FIXME: gpio mask should be model specific */
+ .start = AVILA_GPIO_MASK,
+ .end = AVILA_GPIO_MASK,
+ .flags = 0,
+ .num_resources = ARRAY_SIZE(avila_gpio_resources),
+ .resource = avila_gpio_resources,
+};
-+#endif
+
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
-@@ -199,6 +217,9 @@ static struct platform_device *avila_dev
- #ifdef CONFIG_LEDS_IXP4XX
- &avila_leds,
- #endif
-+#ifdef CONFIG_GPIO_DEVICE
+- &avila_uart
++ &avila_uart,
+ &avila_gpio,
-+#endif
};
- static struct platform_device *avila_eth_devices[] = {
+ static char avila_rtc_probe[] __initdata = "rtc-ds1672.probe=0,0x68 ";
Index: linux-2.6.24.2/include/asm-arm/arch-ixp4xx/avila.h
===================================================================
--- linux-2.6.24.2.orig/include/asm-arm/arch-ixp4xx/avila.h
+++ linux-2.6.24.2/include/asm-arm/arch-ixp4xx/avila.h
-@@ -38,3 +38,6 @@
-
- /* User LED */
- #define AVILA_LED_USER_GPIO 3
+@@ -39,3 +39,6 @@
+ /* User LEDs */
+ #define AVILA_GW23XX_LED_USER_GPIO 3
+ #define AVILA_GW23X7_LED_USER_GPIO 4
+
+/* gpio mask used by platform device */
-+#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9)
++#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9)
--- /dev/null
+Index: linux-2.6.24.2/arch/arm/mach-ixp4xx/avila-setup.c
+===================================================================
+--- linux-2.6.24.2.orig/arch/arm/mach-ixp4xx/avila-setup.c
++++ linux-2.6.24.2/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -276,6 +276,7 @@ static void __init avila_gw2345_setup(vo
+
+ static void __init avila_gw2347_setup(void)
+ {
++ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
+ platform_device_register(&avila_npeb_device);
+
+ avila_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
+@@ -310,6 +311,7 @@ static void __init avila_gw2355_setup(vo
+
+ static void __init avila_gw2357_setup(void)
+ {
++ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
+ platform_device_register(&avila_npeb_device);
+
+ avila_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
+Index: linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c
+===================================================================
+--- linux-2.6.24.2.orig/drivers/net/arm/ixp4xx_eth.c
++++ linux-2.6.24.2/drivers/net/arm/ixp4xx_eth.c
+@@ -347,6 +347,14 @@ static void phy_reset(struct net_device
+ return;
+ }
+
++ if (port->plat->quirks & IXP4XX_ETH_QUIRK_GW23X7) {
++ mdio_write(dev, 1, 0x19,
++ (mdio_read(dev, 1, 0x19) & 0xfffe) | 0x8000);
++
++ printk(KERN_DEBUG "%s: phy_id of the DP83848 changed to 0\n",
++ dev->name);
++ }
++
+ /* restart auto negotiation */
+ bmcr = mdio_read(dev, phy_id, MII_BMCR);
+ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
+Index: linux-2.6.24.2/include/asm-arm/arch-ixp4xx/platform.h
+===================================================================
+--- linux-2.6.24.2.orig/include/asm-arm/arch-ixp4xx/platform.h
++++ linux-2.6.24.2/include/asm-arm/arch-ixp4xx/platform.h
+@@ -115,6 +115,8 @@ struct eth_plat_info {
+ u8 txreadyq;
+ u8 hwaddr[6];
+ u32 phy_mask;
++ u32 quirks;
++#define IXP4XX_ETH_QUIRK_GW23X7 0x00000001
+ };
+
+ /* Information about built-in HSS (synchronous serial) interfaces */
projects / openwrt / staging / jogo.git / commitdiff