In current state there's huge regression on ipq806x target that causes the device to transmit broken/malformed frames that are not corrected/detected by error control mechanisms and other less severe issues.
https://bugs.lede-project.org/index.php?do=details&task_id=1197
This finally had been narrowed down to patch 0071-pcie-qcom-fixes.patch
Meanwhile QSDK contains a handful of commits that add support for ipq806x to upstream qcom pcie driver
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/log/drivers/pci/host/pcie-qcom.c?h=eggplant
Unfortunately qca developers do not bother to push it upstream.
Using those commits instead of lede 0071 patch fixes mentioned issue and probably many others as it seems that corrupted data has been originating within pcie misconfiguration.
Fixes: FS#1197 and probably others
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
--- /dev/null
+From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Tue, 19 Jul 2016 18:44:49 +0530
+Subject: PCI: qcom: Fixed IPQ806x specific clocks
+
+Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++-----
+ 1 file changed, 33 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -53,6 +53,8 @@ struct qcom_pcie_resources_v0 {
+ struct clk *iface_clk;
+ struct clk *core_clk;
+ struct clk *phy_clk;
++ struct clk *aux_clk;
++ struct clk *ref_clk;
+ struct reset_control *pci_reset;
+ struct reset_control *axi_reset;
+ struct reset_control *ahb_reset;
+@@ -160,6 +162,14 @@ static int qcom_pcie_get_resources_v0(st
+ if (IS_ERR(res->phy_clk))
+ return PTR_ERR(res->phy_clk);
+
++ res->aux_clk = devm_clk_get(dev, "aux");
++ if (IS_ERR(res->aux_clk))
++ return PTR_ERR(res->aux_clk);
++
++ res->ref_clk = devm_clk_get(dev, "ref");
++ if (IS_ERR(res->ref_clk))
++ return PTR_ERR(res->ref_clk);
++
+ res->pci_reset = devm_reset_control_get(dev, "pci");
+ if (IS_ERR(res->pci_reset))
+ return PTR_ERR(res->pci_reset);
+@@ -227,6 +237,8 @@ static void qcom_pcie_deinit_v0(struct q
+ clk_disable_unprepare(res->iface_clk);
+ clk_disable_unprepare(res->core_clk);
+ clk_disable_unprepare(res->phy_clk);
++ clk_disable_unprepare(res->aux_clk);
++ clk_disable_unprepare(res->ref_clk);
+ regulator_disable(res->vdda);
+ regulator_disable(res->vdda_phy);
+ regulator_disable(res->vdda_refclk);
+@@ -269,16 +281,28 @@ static int qcom_pcie_init_v0(struct qcom
+ goto err_assert_ahb;
+ }
+
++ ret = clk_prepare_enable(res->core_clk);
++ if (ret) {
++ dev_err(dev, "cannot prepare/enable core clock\n");
++ goto err_clk_core;
++ }
++
+ ret = clk_prepare_enable(res->phy_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable phy clock\n");
+ goto err_clk_phy;
+ }
+
+- ret = clk_prepare_enable(res->core_clk);
++ ret = clk_prepare_enable(res->aux_clk);
+ if (ret) {
+- dev_err(dev, "cannot prepare/enable core clock\n");
+- goto err_clk_core;
++ dev_err(dev, "cannot prepare/enable aux clock\n");
++ goto err_clk_aux;
++ }
++
++ ret = clk_prepare_enable(res->ref_clk);
++ if (ret) {
++ dev_err(dev, "cannot prepare/enable ref clock\n");
++ goto err_clk_ref;
+ }
+
+ ret = reset_control_deassert(res->ahb_reset);
+@@ -327,10 +351,14 @@ static int qcom_pcie_init_v0(struct qcom
+ return 0;
+
+ err_deassert_ahb:
+- clk_disable_unprepare(res->core_clk);
+-err_clk_core:
++ clk_disable_unprepare(res->ref_clk);
++err_clk_ref:
++ clk_disable_unprepare(res->aux_clk);
++err_clk_aux:
+ clk_disable_unprepare(res->phy_clk);
+ err_clk_phy:
++ clk_disable_unprepare(res->core_clk);
++err_clk_core:
+ clk_disable_unprepare(res->iface_clk);
+ err_assert_ahb:
+ regulator_disable(res->vdda_phy);
--- /dev/null
+From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Tue, 19 Jul 2016 18:58:18 +0530
+Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes
+
+Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 24 +++++++++++++++++++-----
+ 1 file changed, 19 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -60,6 +60,7 @@ struct qcom_pcie_resources_v0 {
+ struct reset_control *ahb_reset;
+ struct reset_control *por_reset;
+ struct reset_control *phy_reset;
++ struct reset_control *ext_reset;
+ struct regulator *vdda;
+ struct regulator *vdda_phy;
+ struct regulator *vdda_refclk;
+@@ -190,6 +191,10 @@ static int qcom_pcie_get_resources_v0(st
+ if (IS_ERR(res->phy_reset))
+ return PTR_ERR(res->phy_reset);
+
++ res->ext_reset = devm_reset_control_get(dev, "ext");
++ if (IS_ERR(res->ext_reset))
++ return PTR_ERR(res->ext_reset);
++
+ return 0;
+ }
+
+@@ -234,6 +239,7 @@ static void qcom_pcie_deinit_v0(struct q
+ reset_control_assert(res->ahb_reset);
+ reset_control_assert(res->por_reset);
+ reset_control_assert(res->pci_reset);
++ reset_control_assert(res->ext_reset);
+ clk_disable_unprepare(res->iface_clk);
+ clk_disable_unprepare(res->core_clk);
+ clk_disable_unprepare(res->phy_clk);
+@@ -251,6 +257,12 @@ static int qcom_pcie_init_v0(struct qcom
+ u32 val;
+ int ret;
+
++ ret = reset_control_assert(res->ahb_reset);
++ if (ret) {
++ dev_err(dev, "cannot assert ahb reset\n");
++ return ret;
++ }
++
+ ret = regulator_enable(res->vdda);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda regulator\n");
+@@ -269,16 +281,16 @@ static int qcom_pcie_init_v0(struct qcom
+ goto err_vdda_phy;
+ }
+
+- ret = reset_control_assert(res->ahb_reset);
++ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+- dev_err(dev, "cannot assert ahb reset\n");
+- goto err_assert_ahb;
++ dev_err(dev, "cannot assert ext reset\n");
++ goto err_reset_ext;
+ }
+
+ ret = clk_prepare_enable(res->iface_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable iface clock\n");
+- goto err_assert_ahb;
++ goto err_iface;
+ }
+
+ ret = clk_prepare_enable(res->core_clk);
+@@ -360,7 +372,9 @@ err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+ err_clk_core:
+ clk_disable_unprepare(res->iface_clk);
+-err_assert_ahb:
++err_iface:
++ reset_control_assert(res->ext_reset);
++err_reset_ext:
+ regulator_disable(res->vdda_phy);
+ err_vdda_phy:
+ regulator_disable(res->vdda_refclk);
--- /dev/null
+From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Tue, 19 Jul 2016 19:58:22 +0530
+Subject: PCI: qcom: Fixed IPQ806x PCIE init changes
+
+Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 62 +++++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 53 insertions(+), 9 deletions(-)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -37,7 +37,13 @@
+ #include "pcie-designware.h"
+
+ #define PCIE20_PARF_PHY_CTRL 0x40
++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
++
+ #define PCIE20_PARF_PHY_REFCLK 0x4C
++#define REF_SSP_EN BIT(16)
++#define REF_USE_PAD BIT(12)
++
+ #define PCIE20_PARF_DBI_BASE_ADDR 0x168
+ #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
+ #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
+@@ -48,6 +54,18 @@
+ #define PCIE20_CAP 0x70
+
+ #define PERST_DELAY_US 1000
++/* PARF registers */
++#define PCIE20_PARF_PCS_DEEMPH 0x34
++#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
++#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
++#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
++
++#define PCIE20_PARF_PCS_SWING 0x38
++#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
++#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
++
++#define PCIE20_PARF_CONFIG_BITS 0x50
++#define PHY_RX0_EQ(x) (x << 24)
+
+ struct qcom_pcie_resources_v0 {
+ struct clk *iface_clk;
+@@ -64,6 +82,7 @@ struct qcom_pcie_resources_v0 {
+ struct regulator *vdda;
+ struct regulator *vdda_phy;
+ struct regulator *vdda_refclk;
++ uint8_t phy_tx0_term_offset;
+ };
+
+ struct qcom_pcie_resources_v1 {
+@@ -100,6 +119,16 @@ struct qcom_pcie {
+
+ #define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
+
++static inline void
++writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
++{
++ u32 val = readl(addr);
++
++ val &= ~clear_mask;
++ val |= set_mask;
++ writel(val, addr);
++}
++
+ static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
+ {
+ gpiod_set_value(pcie->reset, 1);
+@@ -195,6 +224,10 @@ static int qcom_pcie_get_resources_v0(st
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
++ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
++ &res->phy_tx0_term_offset))
++ res->phy_tx0_term_offset = 0;
++
+ return 0;
+ }
+
+@@ -254,7 +287,6 @@ static int qcom_pcie_init_v0(struct qcom
+ {
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+ struct device *dev = pcie->pp.dev;
+- u32 val;
+ int ret;
+
+ ret = reset_control_assert(res->ahb_reset);
+@@ -323,15 +355,27 @@ static int qcom_pcie_init_v0(struct qcom
+ goto err_deassert_ahb;
+ }
+
+- /* enable PCIe clocks and resets */
+- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+- val &= ~BIT(0);
+- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+-
+- /* enable external reference clock */
+- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+- val |= BIT(16);
+- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
++ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
++
++ /* Set Tx termination offset */
++ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
++ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
++ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
++
++ /* PARF programming */
++ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
++ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
++ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
++ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
++ writel(PCS_SWING_TX_SWING_FULL(0x78) |
++ PCS_SWING_TX_SWING_LOW(0x78),
++ pcie->parf + PCIE20_PARF_PCS_SWING);
++ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
++
++ /* Enable reference clock */
++ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
++ REF_USE_PAD, REF_SSP_EN);
++
+
+ ret = reset_control_deassert(res->phy_reset);
+ if (ret) {
--- /dev/null
+From e833cdb5c792912d459773cc23153e5d78875d34 Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Tue, 19 Jul 2016 20:05:25 +0530
+Subject: PCIE: designware: Fixed PCI host init
+
+Change-Id: I949b302d77199fc09342acf26b7bb45a7ec467ee
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-designware.c | 9 +++++++--
+ drivers/pci/host/pcie-designware.h | 2 +-
+ drivers/pci/host/pcie-qcom.c | 5 +++--
+ 3 files changed, 11 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
++++ b/drivers/pci/host/pcie-designware.c
+@@ -637,8 +637,13 @@ int dw_pcie_host_init(struct pcie_port *
+ }
+ }
+
+- if (pp->ops->host_init)
+- pp->ops->host_init(pp);
++ if (pp->ops->host_init) {
++ ret = pp->ops->host_init(pp);
++ if (ret) {
++ dev_err(pp->dev, "hostinit failed\n");
++ return 0;
++ }
++ }
+
+ pp->root_bus_nr = pp->busn->start;
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+--- a/drivers/pci/host/pcie-designware.h
++++ b/drivers/pci/host/pcie-designware.h
+@@ -63,7 +63,7 @@ struct pcie_host_ops {
+ int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 val);
+ int (*link_up)(struct pcie_port *pp);
+- void (*host_init)(struct pcie_port *pp);
++ int (*host_init)(struct pcie_port *pp);
+ void (*msi_set_irq)(struct pcie_port *pp, int irq);
+ void (*msi_clear_irq)(struct pcie_port *pp, int irq);
+ phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -515,7 +515,7 @@ static int qcom_pcie_link_up(struct pcie
+ return !!(val & PCI_EXP_LNKSTA_DLLLA);
+ }
+
+-static void qcom_pcie_host_init(struct pcie_port *pp)
++static int qcom_pcie_host_init(struct pcie_port *pp)
+ {
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
+ int ret;
+@@ -541,12 +541,13 @@ static void qcom_pcie_host_init(struct p
+ if (ret)
+ goto err;
+
+- return;
++ return 0;
+ err:
+ qcom_ep_reset_assert(pcie);
+ phy_power_off(pcie->phy);
+ err_deinit:
+ pcie->ops->deinit(pcie);
++ return ret;
+ }
+
+ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
--- /dev/null
+From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Tue, 26 Jul 2016 12:28:31 +0530
+Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
+
+Resolved PCIE EP detection errors caused due to missing iATU programming.
+
+Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 77 insertions(+)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -52,6 +52,29 @@
+ #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
+
+ #define PCIE20_CAP 0x70
++#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
++
++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
++
++#define PCIE20_PLR_IATU_VIEWPORT 0x900
++#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
++#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
++
++#define PCIE20_PLR_IATU_CTRL1 0x904
++#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
++#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
++
++#define PCIE20_PLR_IATU_CTRL2 0x908
++#define PCIE20_PLR_IATU_ENABLE BIT(31)
++
++#define PCIE20_PLR_IATU_LBAR 0x90C
++#define PCIE20_PLR_IATU_UBAR 0x910
++#define PCIE20_PLR_IATU_LAR 0x914
++#define PCIE20_PLR_IATU_LTAR 0x918
++#define PCIE20_PLR_IATU_UTAR 0x91c
++
++#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
+
+ #define PERST_DELAY_US 1000
+ /* PARF registers */
+@@ -163,6 +186,57 @@ static int qcom_pcie_establish_link(stru
+ return dw_pcie_wait_for_link(&pcie->pp);
+ }
+
++static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
++{
++ struct pcie_port *pp = &pcie->pp;
++
++ /*
++ * program and enable address translation region 0 (device config
++ * address space); region type config;
++ * axi config address range to device config address range
++ */
++ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
++ PCIE20_PLR_IATU_REGION_INDEX(0),
++ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
++
++ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
++ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
++ writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
++ writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
++ writel((pp->cfg0_base + pp->cfg0_size - 1),
++ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
++ writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
++ writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
++}
++
++static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
++{
++ struct pcie_port *pp = &pcie->pp;
++
++ /*
++ * program and enable address translation region 2 (device resource
++ * address space); region type memory;
++ * axi device bar address range to device bar address range
++ */
++ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
++ PCIE20_PLR_IATU_REGION_INDEX(2),
++ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
++
++ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
++ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
++ writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
++ writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
++ writel(pp->mem_base + pp->mem_size - 1,
++ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
++ writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
++ writel(upper_32_bits(pp->mem_bus_addr),
++ pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
++
++ /* 256B PCIE buffer setting */
++ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
++}
++
+ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
+ {
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+@@ -404,6 +478,9 @@ static int qcom_pcie_init_v0(struct qcom
+ /* wait for clock acquisition */
+ usleep_range(1000, 1500);
+
++ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
++ qcom_pcie_prog_viewport_mem2_outbound(pcie);
++
+ return 0;
+
+ err_deassert_ahb:
--- /dev/null
+From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Wed, 7 Sep 2016 16:44:28 +0530
+Subject: PCI: qcom: Force GEN1 support
+
+Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -90,6 +90,8 @@
+ #define PCIE20_PARF_CONFIG_BITS 0x50
+ #define PHY_RX0_EQ(x) (x << 24)
+
++#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
++
+ struct qcom_pcie_resources_v0 {
+ struct clk *iface_clk;
+ struct clk *core_clk;
+@@ -138,6 +140,7 @@ struct qcom_pcie {
+ struct phy *phy;
+ struct gpio_desc *reset;
+ struct qcom_pcie_ops *ops;
++ uint32_t force_gen1;
+ };
+
+ #define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
+@@ -477,6 +480,11 @@ static int qcom_pcie_init_v0(struct qcom
+
+ /* wait for clock acquisition */
+ usleep_range(1000, 1500);
++ if (pcie->force_gen1) {
++ writel_relaxed((readl_relaxed(
++ pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
++ pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
++ }
+
+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
+@@ -666,6 +674,8 @@ static int qcom_pcie_probe(struct platfo
+ struct qcom_pcie *pcie;
+ struct pcie_port *pp;
+ int ret;
++ uint32_t force_gen1 = 0;
++ struct device_node *np = pdev->dev.of_node;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+@@ -678,6 +688,9 @@ static int qcom_pcie_probe(struct platfo
+ if (IS_ERR(pcie->reset))
+ return PTR_ERR(pcie->reset);
+
++ of_property_read_u32(np, "force_gen1", &force_gen1);
++ pcie->force_gen1 = force_gen1;
++
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
+ pcie->parf = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->parf))
--- /dev/null
+From edff8f777c6321ca89bb950a382f409c4a126e28 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
+Date: Thu, 15 Dec 2016 17:38:18 +0530
+Subject: pcie: Set PCIE MRRS and MPS to 256B
+
+Set Max Read Request Size and Max Payload Size to 256 bytes,
+per chip team recommendation.
+
+Change-Id: I097004be2ced1b3096ffc10c318aae0b2bb155e8
+Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 37 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+(limited to 'drivers/pci/host/pcie-qcom.c')
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -92,6 +92,14 @@
+
+ #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
+
++#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
++#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
++#define PCIE20_DEV_CAS 0x78
++#define PCIE20_MRRS_MASK __mask(14, 12)
++#define PCIE20_MRRS(x) __set(x, 14, 12)
++#define PCIE20_MPS_MASK __mask(7, 5)
++#define PCIE20_MPS(x) __set(x, 7, 5)
++
+ struct qcom_pcie_resources_v0 {
+ struct clk *iface_clk;
+ struct clk *core_clk;
+@@ -745,6 +753,35 @@ static int qcom_pcie_probe(struct platfo
+ return 0;
+ }
+
++static void qcom_pcie_fixup_final(struct pci_dev *dev)
++{
++ int cap, err;
++ u16 ctl, reg_val;
++
++ cap = pci_pcie_cap(dev);
++ if (!cap)
++ return;
++
++ err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
++
++ if (err)
++ return;
++
++ reg_val = ctl;
++
++ if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1)
++ reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1);
++
++ if (((ctl & PCIE20_MPS_MASK) >> 5) > 1)
++ reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1);
++
++ err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, reg_val);
++
++ if (err)
++ pr_err("pcie config write failed %d\n", err);
++}
++DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
++
+ static const struct of_device_id qcom_pcie_match[] = {
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
+ { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
--- /dev/null
+From b74bab6186131eea09459eedf5d737645a3559c9 Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Thu, 22 Dec 2016 11:18:45 +0530
+Subject: pcie: qcom: Fixed pcie_phy_clk branch issue
+
+Following backtraces are observed in PCIe deinit operation.
+
+ Hardware name: Qualcomm (Flattened Device Tree)
+ (unwind_backtrace) from [] (show_stack+0x10/0x14)
+ (show_stack) from [] (dump_stack+0x84/0x98)
+ (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8)
+ (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
+ (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120)
+ (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4)
+ (clk_core_disable) from [] (clk_disable+0x24/0x30)
+ (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8)
+ (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8)
+ (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538)
+ (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4)
+
+pcie_phy_clk is generated for PCIe controller itself and the
+GCC controls its branch operation. This error is coming since
+the assert operations turn off the parent clock before branch
+clock. Now this patch moves clk_disable_unprepare before assert
+operations.
+
+Similarly, during probe function, the clock branch operation
+should be done after dessert operation. Currently, it does not
+generate any error since bootloader enables the pcie_phy_clk
+but the same error is coming during probe, if bootloader
+disables pcie_phy_clk.
+
+Change-Id: Ib29c154d10eb64363d9cc982ce5fd8107af5627d
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -352,6 +352,7 @@ static void qcom_pcie_deinit_v0(struct q
+ {
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+
++ clk_disable_unprepare(res->phy_clk);
+ reset_control_assert(res->pci_reset);
+ reset_control_assert(res->axi_reset);
+ reset_control_assert(res->ahb_reset);
+@@ -360,7 +361,6 @@ static void qcom_pcie_deinit_v0(struct q
+ reset_control_assert(res->ext_reset);
+ clk_disable_unprepare(res->iface_clk);
+ clk_disable_unprepare(res->core_clk);
+- clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
+ regulator_disable(res->vdda);
+@@ -416,12 +416,6 @@ static int qcom_pcie_init_v0(struct qcom
+ goto err_clk_core;
+ }
+
+- ret = clk_prepare_enable(res->phy_clk);
+- if (ret) {
+- dev_err(dev, "cannot prepare/enable phy clock\n");
+- goto err_clk_phy;
+- }
+-
+ ret = clk_prepare_enable(res->aux_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+@@ -486,6 +480,12 @@ static int qcom_pcie_init_v0(struct qcom
+ return ret;
+ }
+
++ ret = clk_prepare_enable(res->phy_clk);
++ if (ret) {
++ dev_err(dev, "cannot prepare/enable phy clock\n");
++ goto err_deassert_ahb;
++ }
++
+ /* wait for clock acquisition */
+ usleep_range(1000, 1500);
+ if (pcie->force_gen1) {
+@@ -504,8 +504,6 @@ err_deassert_ahb:
+ err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+ err_clk_aux:
+- clk_disable_unprepare(res->phy_clk);
+-err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+ err_clk_core:
+ clk_disable_unprepare(res->iface_clk);
--- /dev/null
+From 1a9c48123bd09f75562b6a2ee0f0a7b2d533cd45 Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Thu, 22 Dec 2016 11:50:49 +0530
+Subject: pcie: qcom: change duplicate pci reset to phy reset
+
+The deinit issues reset_control_assert for pci twice and
+does not contain phy reset.
+
+Change-Id: Iba849963c7e5f9a2a1063f0e2e89635df70b8a99
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -353,7 +353,7 @@ static void qcom_pcie_deinit_v0(struct q
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+
+ clk_disable_unprepare(res->phy_clk);
+- reset_control_assert(res->pci_reset);
++ reset_control_assert(res->phy_reset);
+ reset_control_assert(res->axi_reset);
+ reset_control_assert(res->ahb_reset);
+ reset_control_assert(res->por_reset);
+++ /dev/null
---- a/drivers/pci/host/pcie-qcom.c
-+++ b/drivers/pci/host/pcie-qcom.c
-@@ -36,8 +36,50 @@
-
- #include "pcie-designware.h"
-
-+/* DBI registers */
-+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
-+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
-+
-+#define PCIE20_PLR_IATU_VIEWPORT 0x900
-+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
-+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
-+
-+#define PCIE20_PLR_IATU_CTRL1 0x904
-+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
-+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
-+
-+#define PCIE20_PLR_IATU_CTRL2 0x908
-+#define PCIE20_PLR_IATU_ENABLE BIT(31)
-+
-+#define PCIE20_PLR_IATU_LBAR 0x90C
-+#define PCIE20_PLR_IATU_UBAR 0x910
-+#define PCIE20_PLR_IATU_LAR 0x914
-+#define PCIE20_PLR_IATU_LTAR 0x918
-+#define PCIE20_PLR_IATU_UTAR 0x91c
-+
-+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
-+
-+/* PARF registers */
-+#define PCIE20_PARF_PCS_DEEMPH 0x34
-+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
-+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
-+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
-+
-+#define PCIE20_PARF_PCS_SWING 0x38
-+#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
-+#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
-+
- #define PCIE20_PARF_PHY_CTRL 0x40
-+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
-+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
-+
- #define PCIE20_PARF_PHY_REFCLK 0x4C
-+#define REF_SSP_EN BIT(16)
-+#define REF_USE_PAD BIT(12)
-+
-+#define PCIE20_PARF_CONFIG_BITS 0x50
-+#define PHY_RX0_EQ(x) (x << 24)
-+
- #define PCIE20_PARF_DBI_BASE_ADDR 0x168
- #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
- #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
-@@ -53,14 +95,18 @@ struct qcom_pcie_resources_v0 {
- struct clk *iface_clk;
- struct clk *core_clk;
- struct clk *phy_clk;
-+ struct clk *aux_clk;
-+ struct clk *ref_clk;
- struct reset_control *pci_reset;
- struct reset_control *axi_reset;
- struct reset_control *ahb_reset;
- struct reset_control *por_reset;
- struct reset_control *phy_reset;
-+ struct reset_control *ext_reset;
- struct regulator *vdda;
- struct regulator *vdda_phy;
- struct regulator *vdda_refclk;
-+ uint8_t phy_tx0_term_offset;
- };
-
- struct qcom_pcie_resources_v1 {
-@@ -82,6 +128,7 @@ struct qcom_pcie;
- struct qcom_pcie_ops {
- int (*get_resources)(struct qcom_pcie *pcie);
- int (*init)(struct qcom_pcie *pcie);
-+ void (*configure)(struct qcom_pcie *pcie);
- void (*deinit)(struct qcom_pcie *pcie);
- };
-
-@@ -160,6 +207,14 @@ static int qcom_pcie_get_resources_v0(st
- if (IS_ERR(res->phy_clk))
- return PTR_ERR(res->phy_clk);
-
-+ res->aux_clk = devm_clk_get(dev, "aux");
-+ if (IS_ERR(res->aux_clk))
-+ return PTR_ERR(res->aux_clk);
-+
-+ res->ref_clk = devm_clk_get(dev, "ref");
-+ if (IS_ERR(res->ref_clk))
-+ return PTR_ERR(res->ref_clk);
-+
- res->pci_reset = devm_reset_control_get(dev, "pci");
- if (IS_ERR(res->pci_reset))
- return PTR_ERR(res->pci_reset);
-@@ -180,6 +235,14 @@ static int qcom_pcie_get_resources_v0(st
- if (IS_ERR(res->phy_reset))
- return PTR_ERR(res->phy_reset);
-
-+ res->ext_reset = devm_reset_control_get(dev, "ext");
-+ if (IS_ERR(res->ext_reset))
-+ return PTR_ERR(res->ext_reset);
-+
-+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
-+ &res->phy_tx0_term_offset))
-+ res->phy_tx0_term_offset = 0;
-+
- return 0;
- }
-
-@@ -223,15 +286,69 @@ static void qcom_pcie_deinit_v0(struct q
- reset_control_assert(res->axi_reset);
- reset_control_assert(res->ahb_reset);
- reset_control_assert(res->por_reset);
-- reset_control_assert(res->pci_reset);
-+ reset_control_assert(res->phy_reset);
-+ reset_control_assert(res->ext_reset);
- clk_disable_unprepare(res->iface_clk);
- clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->phy_clk);
-+ clk_disable_unprepare(res->aux_clk);
-+ clk_disable_unprepare(res->ref_clk);
- regulator_disable(res->vdda);
- regulator_disable(res->vdda_phy);
- regulator_disable(res->vdda_refclk);
- }
-
-+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
-+{
-+ struct pcie_port *pp = &pcie->pp;
-+
-+ /*
-+ * program and enable address translation region 0 (device config
-+ * address space); region type config;
-+ * axi config address range to device config address range
-+ */
-+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
-+ PCIE20_PLR_IATU_REGION_INDEX(0),
-+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
-+
-+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
-+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
-+ writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
-+ writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
-+ writel((pp->cfg0_base + pp->cfg0_size - 1),
-+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
-+ writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
-+ writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
-+}
-+
-+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
-+{
-+ struct pcie_port *pp = &pcie->pp;
-+
-+ /*
-+ * program and enable address translation region 2 (device resource
-+ * address space); region type memory;
-+ * axi device bar address range to device bar address range
-+ */
-+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
-+ PCIE20_PLR_IATU_REGION_INDEX(2),
-+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
-+
-+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
-+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
-+ writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
-+ writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
-+ writel(pp->mem_base + pp->mem_size - 1,
-+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
-+ writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
-+ writel(upper_32_bits(pp->mem_bus_addr),
-+ pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
-+
-+ /* 256B PCIE buffer setting */
-+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
-+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
-+}
-+
- static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
- {
- struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
-@@ -260,13 +377,19 @@ static int qcom_pcie_init_v0(struct qcom
- ret = reset_control_assert(res->ahb_reset);
- if (ret) {
- dev_err(dev, "cannot assert ahb reset\n");
-- goto err_assert_ahb;
-+ goto err_assert_reset;
-+ }
-+
-+ ret = reset_control_deassert(res->ext_reset);
-+ if (ret) {
-+ dev_err(dev, "cannot deassert ext reset\n");
-+ goto err_assert_reset;
- }
-
- ret = clk_prepare_enable(res->iface_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable iface clock\n");
-- goto err_assert_ahb;
-+ goto err_assert_reset;
- }
-
- ret = clk_prepare_enable(res->phy_clk);
-@@ -281,22 +404,53 @@ static int qcom_pcie_init_v0(struct qcom
- goto err_clk_core;
- }
-
-+ ret = clk_prepare_enable(res->aux_clk);
-+ if (ret) {
-+ dev_err(dev, "cannot prepare/enable aux clock\n");
-+ goto err_clk_aux;
-+ }
-+
-+ ret = clk_prepare_enable(res->ref_clk);
-+ if (ret) {
-+ dev_err(dev, "cannot prepare/enable ref clock\n");
-+ goto err_clk_ref;
-+ }
-+
- ret = reset_control_deassert(res->ahb_reset);
- if (ret) {
- dev_err(dev, "cannot deassert ahb reset\n");
- goto err_deassert_ahb;
- }
-+ udelay(1);
-
- /* enable PCIe clocks and resets */
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
- val &= ~BIT(0);
- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-
-- /* enable external reference clock */
-+ /* Set Tx termination offset */
-+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-+ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
-+ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset);
-+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-+
-+ /* PARF programming */
-+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
-+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
-+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
-+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
-+ writel(PCS_SWING_TX_SWING_FULL(0x78) |
-+ PCS_SWING_TX_SWING_LOW(0x78),
-+ pcie->parf + PCIE20_PARF_PCS_SWING);
-+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
-+
-+ /* Enable reference clock */
- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
-- val |= BIT(16);
-+ val &= ~REF_USE_PAD;
-+ val |= REF_SSP_EN;
- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
-
-+ /* De-assert PHY, PCIe, POR and AXI resets */
- ret = reset_control_deassert(res->phy_reset);
- if (ret) {
- dev_err(dev, "cannot deassert phy reset\n");
-@@ -327,12 +481,16 @@ static int qcom_pcie_init_v0(struct qcom
- return 0;
-
- err_deassert_ahb:
-+ clk_disable_unprepare(res->ref_clk);
-+err_clk_ref:
-+ clk_disable_unprepare(res->aux_clk);
-+err_clk_aux:
- clk_disable_unprepare(res->core_clk);
- err_clk_core:
- clk_disable_unprepare(res->phy_clk);
- err_clk_phy:
- clk_disable_unprepare(res->iface_clk);
--err_assert_ahb:
-+err_assert_reset:
- regulator_disable(res->vdda_phy);
- err_vdda_phy:
- regulator_disable(res->vdda_refclk);
-@@ -342,6 +500,12 @@ err_refclk:
- return ret;
- }
-
-+static void qcom_pcie_configure_v0(struct qcom_pcie *pcie)
-+{
-+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
-+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
-+}
-+
- static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
- {
- struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
-@@ -455,6 +619,9 @@ static void qcom_pcie_host_init(struct p
- if (ret)
- goto err;
-
-+ if (pcie->ops->init)
-+ pcie->ops->init(pcie);
-+
- return;
- err:
- qcom_ep_reset_assert(pcie);
-@@ -486,6 +653,7 @@ static struct pcie_host_ops qcom_pcie_dw
- static const struct qcom_pcie_ops ops_v0 = {
- .get_resources = qcom_pcie_get_resources_v0,
- .init = qcom_pcie_init_v0,
-+ .configure = qcom_pcie_configure_v0,
- .deinit = qcom_pcie_deinit_v0,
- };
-
projects / openwrt / staging / noltari.git / commitdiff