Tegra: memctrl_v2: fix software logic to check "flush complete"

This patch fixes the logic to check if the command written to the
MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module.

Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index e0e67d5c125619302d30d8b29820c65a3fd79a05..76e21f6db253849d227e1a3fbcafc724a146a4eb 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -254,32 +254,12 @@ static void tegra_memctrl_reconfig_mss_clients(void)
        wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
        tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
 
-       /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
-       do {
-               val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
-       } while ((val & wdata_0) != wdata_0);
-
-       /* Wait one more time due to SW WAR for known legacy issue */
-       do {
-               val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
-       } while ((val & wdata_0) != wdata_0);
-
        val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
        assert(val == wdata_1);
 
        wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
        tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
 
-       /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
-       do {
-               val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
-       } while ((val & wdata_1) != wdata_1);
-
-       /* Wait one more time due to SW WAR for known legacy issue */
-       do {
-               val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
-       } while ((val & wdata_1) != wdata_1);
-
 #endif
 }