[TG3]: Add nvram detection for 5752

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a94631af21cd5a10bddf164ff7736c0b0eb5fa15..dbdd3ecafdc1a003e1a74415f89d88f955d895a1 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7096,6 +7096,63 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
        }
 }
 
+static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
+{
+       u32 nvcfg1;
+
+       nvcfg1 = tr32(NVRAM_CFG1);
+
+       switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+               case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
+               case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
+                       tp->nvram_jedecnum = JEDEC_ATMEL;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       break;
+               case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
+                       tp->nvram_jedecnum = JEDEC_ATMEL;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                       break;
+               case FLASH_5752VENDOR_ST_M45PE10:
+               case FLASH_5752VENDOR_ST_M45PE20:
+               case FLASH_5752VENDOR_ST_M45PE40:
+                       tp->nvram_jedecnum = JEDEC_ST;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                       break;
+       }
+
+       if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
+               switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
+                       case FLASH_5752PAGE_SIZE_256:
+                               tp->nvram_pagesize = 256;
+                               break;
+                       case FLASH_5752PAGE_SIZE_512:
+                               tp->nvram_pagesize = 512;
+                               break;
+                       case FLASH_5752PAGE_SIZE_1K:
+                               tp->nvram_pagesize = 1024;
+                               break;
+                       case FLASH_5752PAGE_SIZE_2K:
+                               tp->nvram_pagesize = 2048;
+                               break;
+                       case FLASH_5752PAGE_SIZE_4K:
+                               tp->nvram_pagesize = 4096;
+                               break;
+                       case FLASH_5752PAGE_SIZE_264:
+                               tp->nvram_pagesize = 264;
+                               break;
+               }
+       }
+       else {
+               /* For eeprom, set pagesize to maximum eeprom size */
+               tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
+
+               nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
+               tw32(NVRAM_CFG1, nvcfg1);
+       }
+}
+
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 static void __devinit tg3_nvram_init(struct tg3 *tp)
 {
@@ -7128,7 +7185,11 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
                        tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
                }
 
-               tg3_get_nvram_info(tp);
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+                       tg3_get_5752_nvram_info(tp);
+               else
+                       tg3_get_nvram_info(tp);
+
                tg3_get_nvram_size(tp);
 
                if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 548f469e9500720b82d9c748ce1b6e69be610e1a..261c2db7ce17c27d71c6e196e6e8a7b4c8d15d05 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1399,6 +1399,20 @@
 #define  FLASH_VENDOR_SAIFUN            0x01000003
 #define  FLASH_VENDOR_SST_SMALL                 0x00000001
 #define  FLASH_VENDOR_SST_LARGE                 0x02000001
+#define  NVRAM_CFG1_5752VENDOR_MASK     0x03c00003
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ    0x00000000
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ   0x02000000
+#define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED  0x02000003
+#define  FLASH_5752VENDOR_ST_M45PE10    0x02400000
+#define  FLASH_5752VENDOR_ST_M45PE20    0x02400002
+#define  FLASH_5752VENDOR_ST_M45PE40    0x02400001
+#define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
+#define  FLASH_5752PAGE_SIZE_256        0x00000000
+#define  FLASH_5752PAGE_SIZE_512        0x10000000
+#define  FLASH_5752PAGE_SIZE_1K                 0x20000000
+#define  FLASH_5752PAGE_SIZE_2K                 0x30000000
+#define  FLASH_5752PAGE_SIZE_4K                 0x40000000
+#define  FLASH_5752PAGE_SIZE_264        0x50000000
 #define NVRAM_CFG2                     0x00007018
 #define NVRAM_CFG3                     0x0000701c
 #define NVRAM_SWARB                    0x00007020