e1000e: Fix queue interrupt re-raising in Other interrupt
authorBenjamin Poirier <bpoirier@suse.com>
Thu, 8 Feb 2018 06:47:13 +0000 (15:47 +0900)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Mon, 5 Mar 2018 18:06:39 +0000 (10:06 -0800)
Restores the ICS write for Rx/Tx queue interrupts which was present before
commit 16ecba59bc33 ("e1000e: Do not read ICR in Other interrupt", v4.5-rc1)
but was not restored in commit 4aea7a5c5e94
("e1000e: Avoid receiver overrun interrupt bursts", v4.15-rc1).

This re-raises the queue interrupts in case the txq or rxq bits were set in
ICR and the Other interrupt handler read and cleared ICR before the queue
interrupt was raised.

Fixes: 4aea7a5c5e94 ("e1000e: Avoid receiver overrun interrupt bursts")
Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/e1000e/netdev.c

index 3b36efa6228d2b79ff1843c7132508c0af80087c..2c9609bee2ae4f7db1026291179a4c8e672de973 100644 (file)
@@ -1919,6 +1919,9 @@ static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
        icr = er32(ICR);
        ew32(ICR, E1000_ICR_OTHER);
 
+       if (icr & adapter->eiac_mask)
+               ew32(ICS, (icr & adapter->eiac_mask));
+
        if (icr & E1000_ICR_LSC) {
                ew32(ICR, E1000_ICR_LSC);
                hw->mac.get_link_status = true;