bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
-#ifdef CONFIG_IP860
- bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
- bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
-#elif defined CONFIG_MPC8220
+#ifdef CONFIG_SYS_SRAM_BASE
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
#else
- bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
- bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
+ bd->bi_sramstart = 0;
+ bd->bi_sramsize = 0;
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define SRAM_BASE 0x80000000 /* SRAM base address */
-#define SRAM_END 0x801FFFFF
/*----------------------------------------------------------------------*/
/* CPC45 Memory Map */
/*----------------------------------------------------------------------*/
#define SRAM_BASE 0x80000000 /* SRAM base address */
+#define SRAM_END 0x801FFFFF
#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
#define BCSR_BASE 0x80600000 /* board control / status registers */
#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
+#define CONFIG_SYS_SRAM_BASE SRAM_BASE
+#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers */
#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
+#define CONFIG_SYS_SRAM_BASE SRAM_BASE
+#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE
/*
* BR4/OR4 - Board Control & Status (8 bit)