ar71xx_eth0_data.phy_mask = 0x0;
ar71xx_eth0_data.speed = SPEED_100;
ar71xx_eth0_data.duplex = DUPLEX_FULL;
+ ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000;
+ ar71xx_eth0_data.fifo_cfg2 = 0x00001fff;
+ ar71xx_eth0_data.fifo_cfg3 = 0x008001ff;
/* LAN ports */
ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
ar71xx_eth1_data.phy_mask = 0x0;
ar71xx_eth1_data.speed = SPEED_1000;
ar71xx_eth1_data.duplex = DUPLEX_FULL;
+ ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000;
+ ar71xx_eth1_data.fifo_cfg2 = 0x00001fff;
+ ar71xx_eth1_data.fifo_cfg3 = 0x008001ff;
ar71xx_add_device_eth(1);
ar71xx_add_device_eth(0);
ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ar71xx_eth0_data.phy_mask = 0;
-
ar71xx_eth0_data.speed = SPEED_100;
ar71xx_eth0_data.duplex = DUPLEX_FULL;
+ ar71xx_eth0_data.fifo_cfg1 = 0x0010ffff;
+ ar71xx_eth0_data.fifo_cfg2 = 0x015500aa;
+ ar71xx_eth0_data.fifo_cfg3 = 0x01f00140;
ar71xx_add_device_eth(0);
ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
ar71xx_eth1_data.phy_mask = 0;
-
ar71xx_eth1_data.speed = SPEED_1000;
ar71xx_eth1_data.duplex = DUPLEX_FULL;
+ ar71xx_eth1_data.fifo_cfg1 = 0x0010ffff;
+ ar71xx_eth1_data.fifo_cfg2 = 0x015500aa;
+ ar71xx_eth1_data.fifo_cfg3 = 0x01f00140;
ar71xx_add_device_eth(1);
}
void (* ddr_flush)(void);
void (* set_pll)(int speed);
+
+ u32 fifo_cfg1;
+ u32 fifo_cfg2;
+ u32 fifo_cfg3;
};
struct ag71xx_mdio_platform_data {
/* setup FIFO configuration registers */
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+ if (pdata->is_ar724x) {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+ } else {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+ }
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
return;
}
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
- pdata->is_ar91xx ? 0x780fff : 0x008001ff);
+ if (pdata->is_ar91xx)
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
+ else if (pdata->is_ar724x)
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
+ else
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
if (pdata->set_pll)
pdata->set_pll(ag->speed);