coresight: tmc: waiting for TMCReady bit before programming

According to the TRM before programming the TMC in circular
buffer mode (and that for any configuration, ETB, ETR, ETF),
the TMCReady bit in the status register has to be set.

This patch adds a check to make sure the state machine is in
a state where it can be configured, and complains otherwise.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 3f646e29a99ba4808a13dcb6ada270ef946a2900..66fa7736d12f519edf4956fd5fda5a9987a8eedf 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -180,6 +180,9 @@ static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
 
        CS_UNLOCK(drvdata->base);
 
+       /* Wait for TMCSReady bit to be set */
+       tmc_wait_for_tmcready(drvdata);
+
        writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
        writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
                       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
@@ -201,6 +204,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 
        CS_UNLOCK(drvdata->base);
 
+       /* Wait for TMCSReady bit to be set */
+       tmc_wait_for_tmcready(drvdata);
+
        writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
        writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 
@@ -230,6 +236,9 @@ static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
 {
        CS_UNLOCK(drvdata->base);
 
+       /* Wait for TMCSReady bit to be set */
+       tmc_wait_for_tmcready(drvdata);
+
        writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
        writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
                       drvdata->base + TMC_FFCR);