MIPS: add support for Broadcom MIPS BCM6318 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi
new file mode 100644 (file)
index 0000000..54964a7
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6318.dtsi
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6318-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power-domain/bcm6318-power-domain.h>
+#include <dt-bindings/reset/bcm6318-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,bcm6318";
+
+       aliases {
+               spi0 = &spi;
+       };
+
+       cpus {
+               reg = <0x10000000 0x4>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               u-boot,dm-pre-reloc;
+
+               cpu@0 {
+                       compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <0>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <250000000>;
+               };
+
+               periph_osc: periph-osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               periph_clk: periph-clk {
+                       compatible = "brcm,bcm6345-clk";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+       };
+
+       ubus {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               periph_rst: reset-controller@10000010 {
+                       compatible = "brcm,bcm6345-reset";
+                       reg = <0x10000010 0x4>;
+                       #reset-cells = <1>;
+               };
+
+               wdt: watchdog@10000068 {
+                       compatible = "brcm,bcm6345-wdt";
+                       reg = <0x10000068 0xc>;
+                       clocks = <&periph_osc>;
+               };
+
+               wdt-reboot {
+                       compatible = "wdt-reboot";
+                       wdt = <&wdt>;
+               };
+
+               pll_cntl: syscon@10000074 {
+                       compatible = "syscon";
+                       reg = <0x10000074 0x4>;
+               };
+
+               syscon-reboot {
+                       compatible = "syscon-reboot";
+                       regmap = <&pll_cntl>;
+                       offset = <0x0>;
+                       mask = <0x1>;
+               };
+
+               gpio1: gpio-controller@10000080 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x10000080 0x4>, <0x10000088 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <18>;
+
+                       status = "disabled";
+               };
+
+               gpio0: gpio-controller@10000084 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               uart0: serial@10000100 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000100 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               leds: led-controller@10000200 {
+                       compatible = "brcm,bcm6328-leds";
+                       reg = <0x10000200 0x28>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               periph_pwr: power-controller@100008e8 {
+                       compatible = "brcm,bcm6328-power-domain";
+                       reg = <0x100008e8 0x4>;
+                       #power-domain-cells = <1>;
+               };
+
+               spi: spi@10003000 {
+                       compatible = "brcm,bcm6328-hsspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x10003000 0x600>;
+                       clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       resets = <&periph_rst BCM6318_RST_SPI>;
+                       spi-max-frequency = <33333334>;
+                       num-cs = <3>;
+
+                       status = "disabled";
+               };
+
+               memory-controller@10004000 {
+                       compatible = "brcm,bcm6318-mc";
+                       reg = <0x10004000 0x38>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};

diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 936b67f5f2098b27e55e83963ad97bc7055029c3..c9b56f5ca7fd2041174429c85eb9184ce6c81ead 100644 (file)
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -6,6 +6,7 @@ config SYS_MALLOC_F_LEN
 
 config SYS_SOC
        default "bcm3380" if SOC_BMIPS_BCM3380
+       default "bcm6318" if SOC_BMIPS_BCM6318
        default "bcm6328" if SOC_BMIPS_BCM6328
        default "bcm6338" if SOC_BMIPS_BCM6338
        default "bcm6348" if SOC_BMIPS_BCM6348
@@ -27,6 +28,17 @@ config SOC_BMIPS_BCM3380
        help
          This supports BMIPS BCM3380 family.
 
+config SOC_BMIPS_BCM6318
+       bool "BMIPS BCM6318 family"
+       select SUPPORTS_BIG_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select MIPS_TUNE_4KC
+       select MIPS_L1_CACHE_SHIFT_4
+       select SWAP_IO_SPACE
+       select SYSRESET_SYSCON
+       help
+         This supports BMIPS BCM6318 family.
+
 config SOC_BMIPS_BCM6328
        bool "BMIPS BCM6328 family"
        select SUPPORTS_BIG_ENDIAN

diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
new file mode 100644 (file)
index 0000000..454a7b7
--- /dev/null
+++ b/include/configs/bmips_bcm6318.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6318_H
+#define __CONFIG_BMIPS_BCM6318_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ     166500000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET      0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6318_H */

diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h
new file mode 100644 (file)
index 0000000..1e3dc16
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6318-clock.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
+#define __DT_BINDINGS_CLOCK_BCM6318_H
+
+#define BCM6318_CLK_ADSL_ASB   0
+#define BCM6318_CLK_USB_ASB    1
+#define BCM6318_CLK_MIPS_ASB   2
+#define BCM6318_CLK_PCIE_ASB   3
+#define BCM6318_CLK_PHYMIPS_ASB        4
+#define BCM6318_CLK_ROBOSW_ASB 5
+#define BCM6318_CLK_SAR_ASB    6
+#define BCM6318_CLK_SDR_ASB    7
+#define BCM6318_CLK_SWREG_ASB  8
+#define BCM6318_CLK_PERIPH_ASB 9
+#define BCM6318_CLK_CPUBUS160  10
+#define BCM6318_CLK_ADSL       11
+#define BCM6318_CLK_SAR125     12
+#define BCM6318_CLK_MIPS       13
+#define BCM6318_CLK_PCIE       14
+#define BCM6318_CLK_ROBOSW250  16
+#define BCM6318_CLK_ROBOSW025  17
+#define BCM6318_CLK_SDR                19
+#define BCM6318_CLK_USB                20
+#define BCM6318_CLK_HSSPI      25
+#define BCM6318_CLK_PCIE25     27
+#define BCM6318_CLK_PHYMIPS    28
+#define BCM6318_CLK_AFE                29
+#define BCM6318_CLK_QPROC      30
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */

diff --git a/include/dt-bindings/power-domain/bcm6318-power-domain.h b/include/dt-bindings/power-domain/bcm6318-power-domain.h
new file mode 100644 (file)
index 0000000..fb075d2
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6318-power-domain.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
+
+#define BCM6318_PWR_PCIE       0
+#define BCM6318_PWR_USB                1
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */

diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h
new file mode 100644 (file)
index 0000000..781d7fb
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6318-reset.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6318_H
+#define __DT_BINDINGS_RESET_BCM6318_H
+
+#define BCM6318_RST_SPI                0
+#define BCM6318_RST_EPHY       1
+#define BCM6318_RST_SAR                2
+#define BCM6318_RST_ENETSW     3
+#define BCM6318_RST_USBD       4
+#define BCM6318_RST_USBH       5
+#define BCM6318_RST_PCIE_CORE  6
+#define BCM6318_RST_PCIE       7
+#define BCM6318_RST_PCIE_EXT   8
+#define BCM6318_RST_PCIE_HARD  9
+#define BCM6318_RST_ADSL       10
+#define BCM6318_RST_PHYMIPS    11
+#define BCM6318_RST_HOSTMIPS   11
+
+#endif /* __DT_BINDINGS_RESET_BCM6318_H */