bcm6838: add initial support

This adds the initial support of the Broadcom BCM6838 SoC familly,
only cpu, dram, uart and leds are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi
new file mode 100644 (file)
index 0000000..d365d0f
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6838.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,bcm6838";
+
+       cpus {
+               reg = <0x14e00000 0x4>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               u-boot,dm-pre-reloc;
+
+               cpu@0 {
+                       compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <0>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               cpu@1 {
+                       compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <1>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               periph_osc: periph-osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       ubus {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               memory: memory-controller@12000000 {
+                       compatible = "brcm,bcm6328-mc";
+                       reg = <0x12000000 0x1000>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               uart0: serial@14e00500 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x14e00500 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               leds: led-controller@14e00f00 {
+                       compatible = "brcm,bcm6328-leds";
+                       reg = <0x14e00f00 0x28>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 5968d5345ed7c33b0f0190a1853a4cb258f6672e..ce02028578104e2f798b94b2c7d115622281b785 100644 (file)
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -14,6 +14,7 @@ config SYS_SOC
        default "bcm6368" if SOC_BMIPS_BCM6368
        default "bcm6362" if SOC_BMIPS_BCM6362
        default "bcm63268" if SOC_BMIPS_BCM63268
+       default "bcm6838" if SOC_BMIPS_BCM6838
 
 choice
        prompt "Broadcom MIPS SoC select"
@@ -118,6 +119,18 @@ config SOC_BMIPS_BCM63268
          This supports BMIPS BCM63268 family including BCM63168, BCM63169,
          BCM63268 and BCM63269.
 
+config SOC_BMIPS_BCM6838
+       bool "BMIPS BCM6838 family"
+       select MIPS_L1_CACHE_SHIFT_4
+       select MIPS_TUNE_4KC
+       select SUPPORTS_BIG_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select SWAP_IO_SPACE
+       select SYSRESET_SYSCON
+       help
+         This supports BMIPS BCM6838 family including BCM68380, BCM68381,
+         and BCM68385.
+
 endchoice
 
 choice

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 78560b0fb4ffdaef01c369ae0e6709df1845cfcb..fc047473f5bc9eb163813ee5d90ee894e3394588 100644 (file)
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -66,6 +66,10 @@
 #define STRAPBUS_63268_FCVO_SHIFT      21
 #define STRAPBUS_63268_FCVO_MASK       (0xf << STRAPBUS_63268_FCVO_SHIFT)
 
+#define REG_BCM6838_OTP_BRCMBITS0      0x440
+#define VIPER_6838_FREQ_SHIFT          18
+#define VIPER_6838_FREQ_MASK           (0x7 << VIPER_6838_FREQ_SHIFT)
+
 struct bmips_cpu_priv;
 
 struct bmips_cpu_hw {
@@ -272,6 +276,26 @@ static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
        }
 }
 
+static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+       unsigned int mips_viper_freq;
+
+       mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
+       mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
+               >> VIPER_6838_FREQ_SHIFT;
+
+       switch (mips_viper_freq) {
+       case 0x0:
+               return 600000000;
+       case 0x1:
+               return 400000000;
+       case 0x2:
+               return 240000000;
+       default:
+               return 0;
+       }
+}
+
 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 {
        u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
@@ -346,6 +370,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
        .get_cpu_count = bcm6358_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
+       .get_cpu_desc = bmips_short_cpu_desc,
+       .get_cpu_freq = bcm6838_get_cpu_freq,
+       .get_cpu_count = bcm6358_get_cpu_count,
+};
+
 /* Generic CPU Ops */
 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
 {
@@ -444,6 +474,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
        }, {
                .compatible = "brcm,bcm63268-cpu",
                .data = (ulong)&bmips_cpu_bcm63268,
+       }, {
+               .compatible = "brcm,bcm6838-cpu",
+               .data = (ulong)&bmips_cpu_bcm6838,
        },
        { /* sentinel */ }
 };

diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h
new file mode 100644 (file)
index 0000000..e79a982
--- /dev/null
+++ b/include/configs/bmips_bcm6838.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6838_H
+#define __CONFIG_BMIPS_BCM6838_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ     160000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET      0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6838_H */