arm64: dts: Add L2-cache DT node for NS2

Recent kernels requires cache hierrachy to be defined via DT hence
this patch updates NS2 DT accordingly.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Sandeep Tripathy <tripathy@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 3c92d92278e5795df4cf7654186959248fc35872..f7591755c37ab740202577b2e5ff1721eeb77605 100644 (file)
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -50,6 +50,7 @@
                        reg = <0 0>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0 0x84b00000>;
+                       next-level-cache = <&CLUSTER0_L2>;
                };
 
                cpu@1 {
@@ -58,6 +59,7 @@
                        reg = <0 1>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0 0x84b00000>;
+                       next-level-cache = <&CLUSTER0_L2>;
                };
 
                cpu@2 {
@@ -66,6 +68,7 @@
                        reg = <0 2>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0 0x84b00000>;
+                       next-level-cache = <&CLUSTER0_L2>;
                };
 
                cpu@3 {
@@ -74,6 +77,11 @@
                        reg = <0 3>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0 0x84b00000>;
+                       next-level-cache = <&CLUSTER0_L2>;
+               };
+
+               CLUSTER0_L2: l2-cache@000 {
+                       compatible = "cache";
                };
        };