struct amdgpu_crtc *acrtc;
const struct dc_stream *stream;
struct dc_flip_addrs addr = { {0} };
+ struct dc_surface_update surface_updates[1] = { {0} };
/*
* TODO risk of concurrency issues
acrtc->base.state->event = NULL;
}
- dc_flip_surface_addrs(adev->dm.dc,
- dc_stream_get_status(stream)->surfaces,
- &addr, 1);
+ surface_updates->surface = dc_stream_get_status(stream)->surfaces[0];
+ surface_updates->flip_addr = &addr;
+
+
+ dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, stream);
DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
__func__,
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
struct validate_context *context;
+ bool wait_4_prev_commits = false;
ret = drm_atomic_helper_check(dev, state);
new_stream_count++;
need_to_validate = true;
+ wait_4_prev_commits = true;
break;
}
new_stream_count++;
need_to_validate = true;
+ wait_4_prev_commits = true;
break;
}
set,
set_count,
acrtc->stream);
+ wait_4_prev_commits = true;
}
break;
}
context = dc_get_validate_context(dc, set, set_count);
- if (need_to_validate == false || set_count == 0 || context)
+ if (need_to_validate == false || set_count == 0 || context) {
+
ret = 0;
+ if (wait_4_prev_commits) {
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ struct drm_crtc_state *crtc_state;
+
+ if (acrtc->stream) {
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(crtc_state)) {
+ ret = PTR_ERR(crtc_state);
+ break;
+ }
+ }
+ }
+ }
+ }
+
if (context) {
dc_resource_validate_ctx_destruct(context);
dm_free(context);