docs: openrisc: convert to ReST and add to documentation body

Manually convert the two openRisc documents to ReST, adding them
to the Linux documentation body.

Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>

diff --git a/Documentation/index.rst b/Documentation/index.rst
index 771affb4dd3a639364e7d206d6a49e98972eec96..14ccbc49968337b1f78b136df70f43833541af14 100644 (file)
--- a/Documentation/index.rst
+++ b/Documentation/index.rst
@@ -147,6 +147,7 @@ implementation.
    ia64/index
    m68k/index
    powerpc/index
+   openrisc/index
    parisc/index
    riscv/index
    s390/index

diff --git a/Documentation/openrisc/README b/Documentation/openrisc/README
deleted file mode 100644 (file)
index 777a893..0000000
--- a/Documentation/openrisc/README
+++ /dev/null
@@ -1,110 +0,0 @@
-OpenRISC Linux
-==============
-
-This is a port of Linux to the OpenRISC class of microprocessors; the initial
-target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
-
-For information about OpenRISC processors and ongoing development:
-
-       website         http://openrisc.io
-       email           openrisc@lists.librecores.org
-
----------------------------------------------------------------------
-
-Build instructions for OpenRISC toolchain and Linux
-===================================================
-
-In order to build and run Linux for OpenRISC, you'll need at least a basic
-toolchain and, perhaps, the architectural simulator.  Steps to get these bits
-in place are outlined here.
-
-1) Toolchain
-
-Toolchain binaries can be obtained from openrisc.io or our github releases page.
-Instructions for building the different toolchains can be found on openrisc.io
-or Stafford's toolchain build and release scripts.
-
-       binaries        https://github.com/openrisc/or1k-gcc/releases
-       toolchains      https://openrisc.io/software
-       building        https://github.com/stffrdhrn/or1k-toolchain-build
-
-2) Building
-
-Build the Linux kernel as usual
-
-       make ARCH=openrisc defconfig
-       make ARCH=openrisc
-
-3) Running on FPGA (optional)
-
-The OpenRISC community typically uses FuseSoC to manage building and programming
-an SoC into an FPGA.  The below is an example of programming a De0 Nano
-development board with the OpenRISC SoC.  During the build FPGA RTL is code
-downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
-tools.  Binaries are loaded onto the board with openocd.
-
-       git clone https://github.com/olofk/fusesoc
-       cd fusesoc
-       sudo pip install -e .
-
-       fusesoc init
-       fusesoc build de0_nano
-       fusesoc pgm de0_nano
-
-       openocd -f interface/altera-usb-blaster.cfg \
-               -f board/or1k_generic.cfg
-
-       telnet localhost 4444
-       > init
-       > halt; load_image vmlinux ; reset
-
-4) Running on a Simulator (optional)
-
-QEMU is a processor emulator which we recommend for simulating the OpenRISC
-platform.  Please follow the OpenRISC instructions on the QEMU website to get
-Linux running on QEMU.  You can build QEMU yourself, but your Linux distribution
-likely provides binary packages to support OpenRISC.
-
-       qemu openrisc   https://wiki.qemu.org/Documentation/Platforms/OpenRISC
-
----------------------------------------------------------------------
-
-Terminology
-===========
-
-In the code, the following particles are used on symbols to limit the scope
-to more or less specific processor implementations:
-
-openrisc: the OpenRISC class of processors
-or1k:     the OpenRISC 1000 family of processors
-or1200:   the OpenRISC 1200 processor
-
----------------------------------------------------------------------
-
-History
-========
-
-18. 11. 2003   Matjaz Breskvar (phoenix@bsemi.com)
-       initial port of linux to OpenRISC/or32 architecture.
-        all the core stuff is implemented and seams usable.
-
-08. 12. 2003   Matjaz Breskvar (phoenix@bsemi.com)
-       complete change of TLB miss handling.
-       rewrite of exceptions handling.
-       fully functional sash-3.6 in default initrd.
-       a much improved version with changes all around.
-
-10. 04. 2004   Matjaz Breskvar (phoenix@bsemi.com)
-       alot of bugfixes all over.
-       ethernet support, functional http and telnet servers.
-       running many standard linux apps.
-
-26. 06. 2004   Matjaz Breskvar (phoenix@bsemi.com)
-       port to 2.6.x
-
-30. 11. 2004   Matjaz Breskvar (phoenix@bsemi.com)
-       lots of bugfixes and enhancments.
-       added opencores framebuffer driver.
-
-09. 10. 2010    Jonas Bonn (jonas@southpole.se)
-       major rewrite to bring up to par with upstream Linux 2.6.36

diff --git a/Documentation/openrisc/TODO b/Documentation/openrisc/TODO
deleted file mode 100644 (file)
index c43d4e1..0000000
--- a/Documentation/openrisc/TODO
+++ /dev/null
@@ -1,12 +0,0 @@
-The OpenRISC Linux port is fully functional and has been tracking upstream
-since 2.6.35.  There are, however, remaining items to be completed within
-the coming months.  Here's a list of known-to-be-less-than-stellar items
-that are due for investigation shortly, i.e. our TODO list:
-
--- Implement the rest of the DMA API... dma_map_sg, etc.
-
--- Finish the renaming cleanup... there are references to or32 in the code
-   which was an older name for the architecture.  The name we've settled on is
-   or1k and this change is slowly trickling through the stack.  For the time
-   being, or32 is equivalent to or1k.
-

diff --git a/Documentation/openrisc/index.rst b/Documentation/openrisc/index.rst
new file mode 100644 (file)
index 0000000..748b3ee
--- /dev/null
+++ b/Documentation/openrisc/index.rst
@@ -0,0 +1,18 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================
+OpenRISC Architecture
+=====================
+
+.. toctree::
+   :maxdepth: 2
+
+   openrisc_port
+   todo
+
+.. only::  subproject and html
+
+   Indices
+   =======
+
+   * :ref:`genindex`

diff --git a/Documentation/openrisc/openrisc_port.rst b/Documentation/openrisc/openrisc_port.rst
new file mode 100644 (file)
index 0000000..a18747a
--- /dev/null
+++ b/Documentation/openrisc/openrisc_port.rst
@@ -0,0 +1,121 @@
+==============
+OpenRISC Linux
+==============
+
+This is a port of Linux to the OpenRISC class of microprocessors; the initial
+target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
+
+For information about OpenRISC processors and ongoing development:
+
+       =======         =============================
+       website         http://openrisc.io
+       email           openrisc@lists.librecores.org
+       =======         =============================
+
+---------------------------------------------------------------------
+
+Build instructions for OpenRISC toolchain and Linux
+===================================================
+
+In order to build and run Linux for OpenRISC, you'll need at least a basic
+toolchain and, perhaps, the architectural simulator.  Steps to get these bits
+in place are outlined here.
+
+1) Toolchain
+
+Toolchain binaries can be obtained from openrisc.io or our github releases page.
+Instructions for building the different toolchains can be found on openrisc.io
+or Stafford's toolchain build and release scripts.
+
+       ==========      =================================================
+       binaries        https://github.com/openrisc/or1k-gcc/releases
+       toolchains      https://openrisc.io/software
+       building        https://github.com/stffrdhrn/or1k-toolchain-build
+       ==========      =================================================
+
+2) Building
+
+Build the Linux kernel as usual::
+
+       make ARCH=openrisc defconfig
+       make ARCH=openrisc
+
+3) Running on FPGA (optional)
+
+The OpenRISC community typically uses FuseSoC to manage building and programming
+an SoC into an FPGA.  The below is an example of programming a De0 Nano
+development board with the OpenRISC SoC.  During the build FPGA RTL is code
+downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
+tools.  Binaries are loaded onto the board with openocd.
+
+::
+
+       git clone https://github.com/olofk/fusesoc
+       cd fusesoc
+       sudo pip install -e .
+
+       fusesoc init
+       fusesoc build de0_nano
+       fusesoc pgm de0_nano
+
+       openocd -f interface/altera-usb-blaster.cfg \
+               -f board/or1k_generic.cfg
+
+       telnet localhost 4444
+       > init
+       > halt; load_image vmlinux ; reset
+
+4) Running on a Simulator (optional)
+
+QEMU is a processor emulator which we recommend for simulating the OpenRISC
+platform.  Please follow the OpenRISC instructions on the QEMU website to get
+Linux running on QEMU.  You can build QEMU yourself, but your Linux distribution
+likely provides binary packages to support OpenRISC.
+
+       =============   ======================================================
+       qemu openrisc   https://wiki.qemu.org/Documentation/Platforms/OpenRISC
+       =============   ======================================================
+
+---------------------------------------------------------------------
+
+Terminology
+===========
+
+In the code, the following particles are used on symbols to limit the scope
+to more or less specific processor implementations:
+
+========= =======================================
+openrisc: the OpenRISC class of processors
+or1k:     the OpenRISC 1000 family of processors
+or1200:   the OpenRISC 1200 processor
+========= =======================================
+
+---------------------------------------------------------------------
+
+History
+========
+
+18-11-2003     Matjaz Breskvar (phoenix@bsemi.com)
+       initial port of linux to OpenRISC/or32 architecture.
+        all the core stuff is implemented and seams usable.
+
+08-12-2003     Matjaz Breskvar (phoenix@bsemi.com)
+       complete change of TLB miss handling.
+       rewrite of exceptions handling.
+       fully functional sash-3.6 in default initrd.
+       a much improved version with changes all around.
+
+10-04-2004     Matjaz Breskvar (phoenix@bsemi.com)
+       alot of bugfixes all over.
+       ethernet support, functional http and telnet servers.
+       running many standard linux apps.
+
+26-06-2004     Matjaz Breskvar (phoenix@bsemi.com)
+       port to 2.6.x
+
+30-11-2004     Matjaz Breskvar (phoenix@bsemi.com)
+       lots of bugfixes and enhancments.
+       added opencores framebuffer driver.
+
+09-10-2010    Jonas Bonn (jonas@southpole.se)
+       major rewrite to bring up to par with upstream Linux 2.6.36

diff --git a/Documentation/openrisc/todo.rst b/Documentation/openrisc/todo.rst
new file mode 100644 (file)
index 0000000..420b18b
--- /dev/null
+++ b/Documentation/openrisc/todo.rst
@@ -0,0 +1,15 @@
+====
+TODO
+====
+
+The OpenRISC Linux port is fully functional and has been tracking upstream
+since 2.6.35.  There are, however, remaining items to be completed within
+the coming months.  Here's a list of known-to-be-less-than-stellar items
+that are due for investigation shortly, i.e. our TODO list:
+
+-  Implement the rest of the DMA API... dma_map_sg, etc.
+
+-  Finish the renaming cleanup... there are references to or32 in the code
+   which was an older name for the architecture.  The name we've settled on is
+   or1k and this change is slowly trickling through the stack.  For the time
+   being, or32 is equivalent to or1k.