On some systems, it may be preferred to place the secure EL1/0 vector
table outside of the static placement of the BL31 image itself, for
instance when the latter is located in non-shareable SRAM which does
not tolerate inner shareable WBWA mappings (as is the case on SynQuacer)
So permit the platform to #define SPM_SHIM_EXCEPTIONS_VMA in its
supplementary linker script, in which case it will be used as the
VMA region for the vector table. Note that the LMA does not change,
and it is up to the platform to copy the contents to the right place
at init time.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
"cpu_ops not defined for this platform.")
#if ENABLE_SPM
+#ifndef SPM_SHIM_EXCEPTIONS_VMA
+#define SPM_SHIM_EXCEPTIONS_VMA RAM
+#endif
+
/*
* Exception vectors of the SPM shim layer. They must be aligned to a 2K
* address, but we need to place them in a separate page so that we can set
*(.spm_shim_exceptions)
. = ALIGN(PAGE_SIZE);
__SPM_SHIM_EXCEPTIONS_END__ = .;
- } >RAM
+ } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
+
+ PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
+ . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
#endif
/*