drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode

Blanking packet bit will control whether the transcoder allows the link
to enter the LP state during BLLP regions (assuming there is enough time),
or whether it will keep the link in the HS state with a Blanking Packet

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-7-vandita.kulkarni@intel.com

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index eaf2779b89b8e133d198868a02ce32e09925625c..ae33639d48ba1ff7e224e86c3487ca0f7f75a967 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -685,6 +685,11 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
                        break;
                }
 
+               if (INTEL_GEN(dev_priv) >= 12) {
+                       if (is_vid_mode(intel_dsi))
+                               tmp |= BLANKING_PACKET_ENABLE;
+               }
+
                /* program DSI operation mode */
                if (is_vid_mode(intel_dsi)) {
                        tmp &= ~OP_MODE_MASK;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d760830cfd7b8c4d184dd4429127ff283860dce1..b362ca0663a6069d68ec378c137cd3f6ceab70e4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11021,6 +11021,7 @@ enum skl_power_gate {
 #define  CALIBRATION_DISABLED          (0x0 << 4)
 #define  CALIBRATION_ENABLED_INITIAL_ONLY      (0x2 << 4)
 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC  (0x3 << 4)
+#define  BLANKING_PACKET_ENABLE                (1 << 2)
 #define  S3D_ORIENTATION_LANDSCAPE     (1 << 1)
 #define  EOTP_DISABLED                 (1 << 0)