dm644X: revert cache disable patch

revert commit 913a39e9aa4d935948d41cd727d53f5878414a77 as the
disabling of cache need not be done explicitly. Subsequent
patches to new cache management framework has fixed it.
EMAC issue with cache coherency still exists when cahces are
enabled.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 88c6beeb9daefe2ab404bfae6bbc354993b0c110..2507d79e4ca31079e0d899eb4c81b2541d283026 100644 (file)
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -60,9 +60,6 @@
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */
 #define CONFIG_SYS_HZ                  1000
 #define CONFIG_SOC_DM644X
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_L2CACHE_OFF
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */