#define RD(offset) (readl(mmio + offset.reg))
#define WR(v, offset) (writel(v, mmio + offset.reg))
-static void bdw_forcewake_get(void *mmio)
+static void bdw_forcewake_get(void __iomem *mmio)
{
WR(_MASKED_BIT_DISABLE(0xffff), FORCEWAKE_MT);
.mmap = NULL,
};
-static int expose_firmware_sysfs(struct intel_gvt *gvt, void *mmio)
+static int expose_firmware_sysfs(struct intel_gvt *gvt,
+ void __iomem *mmio)
{
struct intel_gvt_device_info *info = &gvt->device_info;
struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
struct gvt_firmware_header *h;
const struct firmware *fw;
char *path;
- void *mmio, *mem;
+ void __iomem *mmio;
+ void *mem;
int ret;
path = kmalloc(PATH_MAX, GFP_KERNEL);
static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
{
- void *addr = (u64 *)dev_priv->ggtt.gsm + index;
+ void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
u64 pte;
#ifdef readq
static void write_pte64(struct drm_i915_private *dev_priv,
unsigned long index, u64 pte)
{
- void *addr = (u64 *)dev_priv->ggtt.gsm + index;
+ void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
#ifdef writeq
writeq(pte, addr);
static int init_vgpu_opregion(struct intel_vgpu *vgpu, u32 gpa)
{
- void *host_va = vgpu->gvt->opregion.opregion_va;
+ void __iomem *host_va = vgpu->gvt->opregion.opregion_va;
u8 *buf;
int i;